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Difference between revisions of "intel/80486/486dx4-100"
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| name                = Intel i486DX4-100
 
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| image              = I486DX4.jpg

Latest revision as of 15:13, 13 December 2017

Edit Values
Intel i486DX4-100
I486DX4.jpg
A80486DX4-100, S-Spec SX900
General Info
DesignerIntel
ManufacturerIntel
Model Numberi486DX4-100
Part NumberA80486DX4-100,
A80486DX4WB100,
MA80486DX4-100,
TQ80486DX4100,
MQ80486DX4-100,
MQ80486DX4100,
FC80486DX4-100,
FC80486DX4WB100
S-SpecSK050, SK051, SK096, SK851, SX877, SX900, SX908, SK053, SK063, SK099, SL2M9, SX876, SX906
IntroductionMarch 7, 1994 (launched)
ShopAmazon
General Specs
Family80486
Series486DX4
Frequency100 MHz
Bus typeFSB
Bus speed33 MHz
Bus rate33 MT/s
Clock multiplier3
CPUID480, 483
Microarchitecture
Microarchitecture80486
Core Name486DX4
Process600 nm
Transistors1,600,000
TechnologyCMOS
Word Size32 bit
Cores1
Max Memory4 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Power dissipation3.55 W
Vcore3.3 V ± 0.3 V
OP Temperature0 °C – 85 °C

i486DX4-100 was a fourth-generation x86 microprocessor introduced by Intel in 1994. This chip, which is based on the 80486 microarchitecture, had a clock multiplier of x2, x2.5, and x3 with a max operating frequency of 100 MHz, three times the bus frequency. Like the original i486DX, this chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM). The DX4 series had twice as much cache space as the older processors.

Cache[edit]

Main article: 80486 § Cache

The i486dx4-100 was offered with two cache policies. Models that came with a write-back cache were marked by an "&EW" identifier. Models that came with a write-through policy were marked by "&E".

Cache Info [Edit Values]
L1$ 16 KiB
16,384 B
0.0156 MiB
1x16 KiB 4-way set associative (unified, write-through/write-back policy)

Graphics[edit]

This chip had no integrated graphics processing unit.

Features[edit]

Gallery[edit]

See also[edit]

Facts about "i486DX4-100 - Intel"
l1$ description4-way set associative +
l1$ size16 KiB (16,384 B, 0.0156 MiB) +