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Difference between revisions of "amd/k6/amd-k6-200afr"
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Latest revision as of 15:09, 13 December 2017
Edit Values | |
AMD-K6-200AFR | |
General Info | |
Designer | AMD |
Manufacturer | AMD |
Model Number | AMD-K6-200AFR |
Part Number | AMD-K6-200AFR |
Market | Desktop |
Introduction | May, 1997 (announced) May, 1997 (launched) |
Shop | Amazon |
General Specs | |
Family | K6 |
Series | Desktop K6 |
Locked | No |
Frequency | 199.99 MHz |
Bus type | FSB |
Bus speed | 66.66 MHz |
Bus rate | 66.66 MT/s |
Clock multiplier | 3 |
CPUID | 560 |
Microarchitecture | |
Microarchitecture | K6 |
Core Name | 6k86 |
Core Family | 5 |
Core Model | 6 |
Process | 350 nm |
Transistors | 8,800,000 |
Technology | CMOS |
Die | 162 mm² |
Word Size | 32 bit |
Cores | 1 |
Threads | 1 |
Max Memory | 4 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
Power dissipation | 20 W |
Vcore | 2.9 V ± 5% |
VI/O | 3.3 V ± 5% |
Tcase | 0 °C – 70 °C |
Tstorage | -65 °C – 150 °C |
AMD-K6-200AFR was a 32-bit x86 microprocessor designed by AMD and introduced in early 1997. This chip, which was based on AMD's new K6 microarchitecture, operated at 200 MHz and dissipated a maximum of 20 W.
Contents
Cache[edit]
- Main article: K6 § Cache
L2$ can be 256 KiB to 1 MiB, depending on manufacturer and motherboard model. L2$ is off-chip.
Cache Info [Edit Values] | ||
L1I$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
L1D$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
Graphics[edit]
This SoC has no integrated graphics processing unit.
Features[edit]
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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- Auto-power down state
- Stop clock state
Documents[edit]
DataSheet[edit]
- AMD-K6 Processor Data Sheet; Publication #20695 Revision H/0; March 1998
Facts about "AMD-K6-200AFR - AMD"
l1d$ description | 2-way set associative + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |