Semiconductor & Computer Engineering
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Difference between revisions of "Template:planar comp header"
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! style="text-align: right;" | Voltage | ! style="text-align: right;" | Voltage | ||
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| + | ! style="text-align: right;" colspan="2" | Metal Layers | ||
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! style="text-align: right;" colspan="2" | | ! style="text-align: right;" colspan="2" | | ||
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| − | ! style="text-align: right;" colspan="2" | Gate | + | ! style="text-align: right;" colspan="2" | Gate Length (L<sub>g</sub>) |
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! style="text-align: right;" colspan="2" | Contacted Gate Pitch (CPP) | ! style="text-align: right;" colspan="2" | Contacted Gate Pitch (CPP) | ||
Latest revision as of 05:29, 6 April 2017
| Process Name | |
|---|---|
| 1st Production | |
| Lithography | Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Transistor | Type |
| Voltage | |
| Metal Layers | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell | High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell | eDRAM |