Semiconductor & Computer Engineering
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Difference between revisions of "baikal/baikal-t1"
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{{baikal title|Baikal-T1}} | {{baikal title|Baikal-T1}} | ||
| − | {{ | + | {{chip |
| name = Baikal-T1 | | name = Baikal-T1 | ||
| image = Baikal-T1.png | | image = Baikal-T1.png | ||
| Line 6: | Line 6: | ||
| caption = | | caption = | ||
| designer = Baikal Electronics | | designer = Baikal Electronics | ||
| + | | designer 2 = Imagination Technologies | ||
| manufacturer = TSMC | | manufacturer = TSMC | ||
| model number = Baikal-T1 | | model number = Baikal-T1 | ||
| Line 16: | Line 17: | ||
| family = | | family = | ||
| + | | series = Baikal | ||
| locked = | | locked = | ||
| frequency = 1200 MHz | | frequency = 1200 MHz | ||
| + | | bus type = AXI | ||
| isa family = MIPS | | isa family = MIPS | ||
| Line 35: | Line 38: | ||
| electrical = yes | | electrical = yes | ||
| tdp = 5 W | | tdp = 5 W | ||
| + | | tcase min = 0 °C | ||
| + | | tcase max = 70 °C | ||
| packaging = Yes | | packaging = Yes | ||
| Line 47: | Line 52: | ||
| socket 0 type = BGA | | socket 0 type = BGA | ||
}} | }} | ||
| − | + | '''Baikal-T1''' is a {{arch|32}} [[dual-core]] [[MIPS]] [[system on a chip]] introduced by [[Baikal Electronics]] in 2015 for the embedded market. The chip entered mass production in early 2016. The Baikal-T1 incorporates two of [[Imagination Technologies|Imagination]] high-performance {{imgtec|P5600}} cores and is manufactured on [[TSMC]]'s [[28 nm process]]. The Baikal-T1 supports up to 8 GiB of DDR3-1600. | |
The chip consumes less than 5W and can be used in fanless designs. | The chip consumes less than 5W and can be used in fanless designs. | ||
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== Expansions == | == Expansions == | ||
| − | {{ | + | {{expansions |
| − | | pcie revision | + | |pcie revision=3.0 |
| − | | pcie lanes | + | |pcie lanes=4 |
| − | | pcie | + | |pcie config=x4 |
| − | | | + | |usb revision=2.0 |
| − | | | + | |usb rate=480 Mib/s |
| − | | | + | |usb extra=8-bit ULPI PHY |
| − | | | + | |uart=Yes |
| − | | | + | |uart ports=2 |
| − | | | + | |sata revision=3.1 |
| − | | | + | |sata ports=2 |
| − | | | + | |i2c=Yes |
| − | | | + | |i2c ports=2 |
| − | | | + | |gp io=32 bit |
| − | | | + | |jtag=Yes |
| − | | | + | |integrated lan=Yes |
}} | }} | ||
== Networking == | == Networking == | ||
| − | + | {{network | |
| − | {{ | + | |eth opts=Yes |
| − | | | + | |1ge=Yes |
| − | | | + | |1ge ports=2 |
| − | | | + | |10ge=Yes |
| − | | | + | |10ge ports=1 |
| − | | | + | |mii opts=Yes |
| − | | | + | |rgmii=Yes |
| − | + | |rgmii ports=2 | |
| − | | | ||
| − | | | ||
}} | }} | ||
== Block Diagram == | == Block Diagram == | ||
[[File:baikal-t1 block diagram.png|800px]] | [[File:baikal-t1 block diagram.png|800px]] | ||
Latest revision as of 15:10, 13 December 2017
| Edit Values | |
| Baikal-T1 | |
 | |
| General Info | |
| Designer | Baikal Electronics, Imagination Technologies |
| Manufacturer | TSMC |
| Model Number | Baikal-T1 |
| Market | Embedded |
| Introduction | June 1, 2015 (announced) February, 2016 (launched) |
| General Specs | |
| Series | Baikal |
| Frequency | 1200 MHz |
| Bus type | AXI |
| Microarchitecture | |
| ISA | MIPS32 (MIPS) |
| Microarchitecture | P5600 |
| Core Name | P5600 |
| Process | 28 nm |
| Word Size | 32 bit |
| Cores | 2 |
| Threads | 2 |
| Max Memory | 8 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| TDP | 5 W |
| Tcase | 0 °C – 70 °C |
Baikal-T1 is a 32-bit dual-core MIPS system on a chip introduced by Baikal Electronics in 2015 for the embedded market. The chip entered mass production in early 2016. The Baikal-T1 incorporates two of Imagination high-performance P5600 cores and is manufactured on TSMC's 28 nm process. The Baikal-T1 supports up to 8 GiB of DDR3-1600.
The chip consumes less than 5W and can be used in fanless designs.
Cache[edit]
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Networking[edit]
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Networking
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Block Diagram[edit]
Categories:
- all microprocessor models
- microprocessor models by baikal electronics
- microprocessor models by baikal electronics based on p5600
- microprocessor models by imagination technologies
- microprocessor models by imagination technologies based on p5600
- microprocessor models by tsmc
- Articles with invalid parameter in template
Facts about "Baikal-T1 - Baikal Electronics"
| has ecc memory support | true + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 4-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
| max memory channels | 1 + |
| supported memory type | DDR3-1600 + |