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Difference between revisions of "cavium/octeon/cn3120-400bg868-scp"
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{{cavium title|CN3120-400 SCP}} | {{cavium title|CN3120-400 SCP}} | ||
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| name = Cavium CN3120-400 SCP | | name = Cavium CN3120-400 SCP | ||
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| designer = Cavium | | designer = Cavium | ||
| manufacturer = TSMC | | manufacturer = TSMC | ||
− | | model number = CN3120 | + | | model number = CN3120-400 SCP |
| part number = CN3120-400BG868-SCP | | part number = CN3120-400BG868-SCP | ||
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| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
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| market = Embedded | | market = Embedded | ||
| first announced = January 30, 2006 | | first announced = January 30, 2006 | ||
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}} | }} | ||
The '''CN3120-400 SCP''' is a {{arch|64}} [[dual-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates two {{cavium|cnMIPS|l=arch}} cores, operates at 400 MHz. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory. | The '''CN3120-400 SCP''' is a {{arch|64}} [[dual-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates two {{cavium|cnMIPS|l=arch}} cores, operates at 400 MHz. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory. | ||
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|l1d policy=Write-through | |l1d policy=Write-through | ||
|l2 cache=256 KiB | |l2 cache=256 KiB | ||
− | |l2 break= | + | |l2 break=1x256 KiB |
|l2 desc=8-way set associative | |l2 desc=8-way set associative | ||
}} | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR2-667 | ||
+ | |ecc=Yes | ||
+ | |max mem=4 GiB | ||
+ | |controllers=1 | ||
+ | |channels=1 | ||
+ | |width=64 bit | ||
+ | |max bandwidth=4.97 GiB/s | ||
+ | |bandwidth schan=4.97 GiB/s | ||
+ | }} | ||
+ | |||
+ | Optional low-latency controller for content-based processing and meta data | ||
+ | |||
+ | {{memory controller | ||
+ | |type=DDR2-667 | ||
+ | |ecc=Yes | ||
+ | |max mem=2 GiB | ||
+ | |controllers=1 | ||
+ | |channels=1 | ||
+ | |width=16 bit | ||
+ | |max bandwidth=1.24 GiB/s | ||
+ | |bandwidth schan=1.24 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | |pcix width=32 bit | ||
+ | |pcix clock=100 MHz | ||
+ | |pcix rate=381.5 MiB/s | ||
+ | |pci extra=host or slave | ||
+ | |usb revision=2.0 | ||
+ | |usb ports=1 | ||
+ | |usb rate=60 MB/s | ||
+ | |usb extra=host / PHY | ||
+ | |uart=yes | ||
+ | |uart ports=2 | ||
+ | |gp io=Yes | ||
+ | }} | ||
+ | |||
+ | == Networking == | ||
+ | {{network | ||
+ | |mii opts=Yes | ||
+ | |rgmii=yes | ||
+ | |rgmii ports=3 | ||
+ | |gmii=yes | ||
+ | |gmii ports=1 | ||
+ | |pcm=Yes | ||
+ | }} | ||
+ | |||
+ | == Hardware Accelerators == | ||
+ | {{accelerators | ||
+ | |encryption=Yes | ||
+ | |encryption type=DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH | ||
+ | |tcp=Yes | ||
+ | |qos=Yes | ||
+ | }} | ||
+ | |||
+ | == Block diagram == | ||
+ | [[File:octeon cn31xx block diagram.png|750px]] | ||
+ | |||
+ | == Datasheet == | ||
+ | * [[:File:octeon cn31xx product brief.pdf|OCTEON CN31XX Single- and Dual-Core Product Brief]] |
Latest revision as of 16:11, 13 December 2017
Edit Values | |||||||
Cavium CN3120-400 SCP | |||||||
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General Info | |||||||
Designer | Cavium | ||||||
Manufacturer | TSMC | ||||||
Model Number | CN3120-400 SCP | ||||||
Part Number | CN3120-400BG868-SCP | ||||||
Market | Embedded | ||||||
Introduction | January 30, 2006 (announced) May 1, 2006 (launched) | ||||||
General Specs | |||||||
Family | OCTEON | ||||||
Series | CN3100 | ||||||
Frequency | 400 MHz | ||||||
Microarchitecture | |||||||
ISA | MIPS64 (MIPS) | ||||||
Microarchitecture | cnMIPS | ||||||
Core Name | cnMIPS | ||||||
Process | 130 nm | ||||||
Technology | CMOS | ||||||
Word Size | 64 bit | ||||||
Cores | 2 | ||||||
Threads | 2 | ||||||
Max Memory | 4 GiB | ||||||
Multiprocessing | |||||||
Max SMP | 1-Way (Uniprocessor) | ||||||
Packaging | |||||||
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The CN3120-400 SCP is a 64-bit dual-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2006. This processor, which incorporates two cnMIPS cores, operates at 400 MHz. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Optional low-latency controller for content-based processing and meta data
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Networking[edit]
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Networking
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Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
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Hardware Accelerators
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Block diagram[edit]
Datasheet[edit]
Facts about "CN3120-400 SCP - Cavium"
l1$ size | 80 KiB (81,920 B, 0.0781 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |