From WikiChip
Difference between revisions of "cavium/octeon/cn3005-500bg350-scp"
m (Bot: moving all {{mpu}} to {{chip}}) |
|||
(15 intermediate revisions by 2 users not shown) | |||
Line 1: | Line 1: | ||
{{cavium title|CN3005-500 SCP}} | {{cavium title|CN3005-500 SCP}} | ||
− | {{ | + | {{chip |
| name = Cavium CN3005-500 SCP | | name = Cavium CN3005-500 SCP | ||
− | | no image = cn3005-15.png | + | | no image = |
− | + | | image = cn3005-15.png | |
| image size = | | image size = | ||
| caption = | | caption = | ||
| designer = Cavium | | designer = Cavium | ||
| manufacturer = TSMC | | manufacturer = TSMC | ||
− | | model number = CN3005 | + | | model number = CN3005-500 SCP |
| part number = CN3005-500BG350-SCP | | part number = CN3005-500BG350-SCP | ||
− | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
+ | | part number 4 = | ||
| market = Embedded | | market = Embedded | ||
| first announced = January 30, 2006 | | first announced = January 30, 2006 | ||
Line 18: | Line 18: | ||
| last order = | | last order = | ||
| last shipment = | | last shipment = | ||
− | | release price = | + | | release price = |
| family = OCTEON | | family = OCTEON | ||
Line 52: | Line 52: | ||
| max memory addr = | | max memory addr = | ||
− | + | ||
| power = 4 W | | power = 4 W | ||
| v core = | | v core = | ||
Line 89: | Line 89: | ||
| socket 0 type = | | socket 0 type = | ||
}} | }} | ||
− | The '''CN3005-500 SCP''' is a {{arch|64}} [[single-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in early [[2006]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 500 MHz and dissipates 4 Watts. This processors includes a number of hardware security communication accelerators including units for encryption, QoS, and TCP acceleration. | + | The '''CN3005-500 SCP''' is a {{arch|64}} [[single-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in early [[2006]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 500 MHz and dissipates 4 Watts. This processors includes a number of hardware security communication accelerators including units for encryption, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 memory. |
+ | |||
+ | == Cache == | ||
+ | {{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=24 KiB | ||
+ | |l1i cache=16 KiB | ||
+ | |l1i break=1x16 KiB | ||
+ | |l1i desc=2-way set associative | ||
+ | |l1d cache=8 KiB | ||
+ | |l1d break=1x8 KiB | ||
+ | |l1d desc=64-way set associative | ||
+ | |l1d policy=Write-through | ||
+ | |l2 cache=64 KiB | ||
+ | |l2 break=1x64 KiB | ||
+ | |l2 desc=2-way set associative | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR2-533 | ||
+ | |ecc=No | ||
+ | |max mem=2 GiB | ||
+ | |controllers=1 | ||
+ | |channels=1 | ||
+ | |width=16 bit | ||
+ | |max bandwidth=1,017 MiB/s | ||
+ | |bandwidth schan=1,017 MiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | |pci width=32 bit | ||
+ | |pci clock=66.66 MHz | ||
+ | |pci rate=254.31 MiB/s | ||
+ | |pci extra=host or slave | ||
+ | |usb revision=2.0 | ||
+ | |usb ports=1 | ||
+ | |usb rate=60 MB/s | ||
+ | |usb extra=host / PHY | ||
+ | |uart=yes | ||
+ | |uart ports=2 | ||
+ | |gp io=Yes | ||
+ | }} | ||
+ | |||
+ | == Networking == | ||
+ | {{network | ||
+ | |mii opts=Yes | ||
+ | |rgmii=yes | ||
+ | |rgmii ports=1 | ||
+ | |gmii=yes | ||
+ | |gmii ports=1 | ||
+ | }} | ||
+ | |||
+ | == Hardware Accelerators == | ||
+ | {{accelerators | ||
+ | |encryption=Yes | ||
+ | |encryption type=DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH | ||
+ | |tcp=Yes | ||
+ | |qos=Yes | ||
+ | }} | ||
+ | |||
+ | == Block diagram == | ||
+ | [[File:cn3005 block diagram.png|750px]] | ||
+ | |||
+ | == Datasheet == | ||
+ | * [[:File:octeon cn30xx product brief.pdf|OCTEON CN30XX Processors Product Brief]] |
Latest revision as of 16:10, 13 December 2017
Edit Values | |
Cavium CN3005-500 SCP | |
![]() | |
General Info | |
Designer | Cavium |
Manufacturer | TSMC |
Model Number | CN3005-500 SCP |
Part Number | CN3005-500BG350-SCP |
Market | Embedded |
Introduction | January 30, 2006 (announced) May 1, 2006 (launched) |
General Specs | |
Family | OCTEON |
Series | CN3000 |
Frequency | 500 MHz |
Microarchitecture | |
ISA | MIPS64 (MIPS) |
Microarchitecture | cnMIPS |
Core Name | cnMIPS |
Process | 130 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 1 |
Threads | 1 |
Max Memory | 2 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
Power dissipation | 4 W |
The CN3005-500 SCP is a 64-bit single-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in early 2006. This processor, which incorporates a single cnMIPS core, operates at 500 MHz and dissipates 4 Watts. This processors includes a number of hardware security communication accelerators including units for encryption, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 memory.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||
|
Memory controller[edit]
![]() |
Integrated Memory Controller
|
|||||||||||||||
|
Expansions[edit]
![]() |
Expansion Options
|
|||||||||||||||||||||||||
|
Networking[edit]
![]() |
Networking
|
|||||
|
Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
![]() |
Hardware Accelerators
|
|||||||||||
|
Block diagram[edit]
Datasheet[edit]
Facts about "CN3005-500 SCP - Cavium"
l1$ size | 24 KiB (24,576 B, 0.0234 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l2$ description | 2-way set associative + |
l2$ size | 0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + |