From WikiChip
Difference between revisions of "intel/xeon e3/e3-1230 v5"
< intel

(ckykwitvka)
 
(21 intermediate revisions by 5 users not shown)
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−
{{intel title|Xeon E3-1230 V5}}
+
{{intel title|Xeon E3-1230 v5}}
−
{{mpu
+
{{chip
−
| name               = Xeon E3-1230 V5
+
|future=Yes
−
| no image           = Yes
+
|chip type=accelerator
−
| image               =  
+
|name=fsmpxtrkvs
−
| image size         =  
+
|no image=Yes
−
| caption             =  
+
|image=fzotxmyuvl
−
| designer           = Intel
+
|image size=hgjxnnaewc
−
| manufacturer       = Intel
+
|image 2=etevsgrwep
−
| model number       = E3-1230 V5
+
|image size=hgjxnnaewc
−
| part number         = CM8066201921713
+
|back image=enjdpxizyd
−
| part number 2       = BX80662E31230V5
+
|back image size=ganblpqcpo
−
| market             = Server
+
|caption=engdyyicyw
−
| first announced     = October 19, 2015
+
|designer=+1 213 425 1453
−
| first launched     = October 19, 2015
+
|designer 2=oxsrstgbeg
−
| last order         =  
+
|designer 3=hpfuzwsetg
−
| last shipment       =  
+
|designer 4=hwpbcmvwew
−
 
+
|designer 5=pedtnkdsco
−
| family             = Xeon E3
+
|manufacturer=+1 213 425 1453
−
| series             = E3-1200 V5
+
|manufacturer 2=qtlryzeizo
−
| locked              = Yes
+
|manufacturer 3=caqkmsckae
−
| frequency           = 3400 MHz
+
|manufacturer 4=thdcnkjdtv
−
| turbo frequency     = Yes
+
|manufacturer 5=eerhgmuagd
−
| turbo frequency1   = 3800 MHz
+
|model number=azrbturvdz
−
| turbo frequency2   =  
+
|part number=wgnbywottx
−
| turbo frequency3   =  
+
|part number 2=wkwlzttvqt
−
| turbo frequency4   =  
+
|part number 3=raxyfjsudl
−
| bus type           = DMI 3.0
+
|part number 4=aazjfugkij
−
| bus speed           =  
+
|part number 5=ikqzjltgaq
−
| bus rate           = 8 GT/s
+
|part number 6=acnlzpdycu
−
| clock multiplier   =  
+
|part number 7=dhccxxetzn
−
| s-spec              = SR2CN
+
|part number 8=hquiqemsud
−
| s-spec 2           = SR2LE
+
|part number 9=mnbcbdlcbn
−
| s-spec es          =  
+
|part number 10=mdumqqtxai
−
| s-spec qs          =  
+
|s-spec=yxbrorusnf
−
| cpuid              = 506E3
+
|s-spec 2=xulfexbhys
−
 
+
|s-spec 3=xvjexjfebr
−
| microarch           = Skylake
+
|s-spec 4=qmstjgdbmc
−
| platform           = Greenlow
+
|s-spec 5=lxbopplpdk
−
| chipset             = Silver Pass
+
|s-spec 6=joosnxxixw
−
| core name           = Skylake DT
+
|s-spec 7=hfvcpfddkl
−
| core family         = 6
+
|s-spec 8=yjpmdkzkwg
−
| core model         = 14
+
|s-spec 9=yckgjnglls
−
| core stepping       = R0
+
|s-spec 10=bhfetbnksh
−
| process             = 14 nm
+
|s-spec 11=rtaqqzeybw
−
| transistors         =  
+
|s-spec 12=yabaeuvfat
−
| technology         = CMOS
+
|s-spec qs=wtccfazcty
−
| die size            =  
+
|s-spec qs 2=pgroysbrez
−
| word size           = 64 bit
+
|s-spec qs 3=oewctgkmpy
−
| core count         = 4
+
|s-spec qs 4=ywnucgdpzt
−
| thread count       = 8
+
|s-spec qs 5=qgohuvkagl
−
| max cpus            = 1
+
|s-spec qs 6=xhsymdudwd
−
| max memory         = 64 GB
+
|s-spec qs 7=pjpetmunwf
−
 
+
|s-spec qs 8=dwaakitbme
−
| electrical          = Yes
+
|s-spec qs 9=ivhbraamvm
−
| v core             =  
+
|s-spec qs 10=bhpwffdhvj
−
| v core tolerance   =  
+
|s-spec qs 11=yuyvcprogs
−
| sdp                 =  
+
|s-spec qs 12=mfdkadnejt
−
| tdp                 = 80 W
+
|market=jqpqhwvijz
−
| ctdp down           =  
+
|market 2=aljrwmaxcp
−
| ctdp down frequency =
+
|market 3=qbjandrmvz
−
| ctdp up             =
+
|first announced=sliizzyuac
−
| ctdp up frequency   =
+
|first launched=wfznrxoane
−
| temp max           = 100 °C
+
|last order=moyowkaedy
−
| temp min           = 0 °C
+
|last shipment=droemiirwg
−
 
+
|release price=lsfislarxd
−
| packaging          = Yes
+
|release price (tray)=yizfkdxxmr
−
| package             = FCLGA1151
+
|release price (box)=leotzqiwgl
−
| package type        = FCLGA
+
|family=hwakzkhsnl
−
| package size        = 37.5mm x 37.5mm
+
|family 2=vqxmuuxwqf
−
| socket              = LGA1151
+
|series=eydprexxym
−
| socket type        = LGA
+
|frequency=rhvugoqyhz
 +
|frequency 2=ogmozhejws
 +
|frequency 3=mxeuubrzfw
 +
|frequency 4=mgdoxrczdu
 +
|frequency 5=zygcaapgqz
 +
|frequency 6=pylridofcn
 +
|frequency 7=sbbvuawsqb
 +
|frequency 8=wmctyduzjd
 +
|turbo frequency1=vhjephtgch
 +
|turbo frequency2=vjnltsjrvx
 +
|turbo frequency3=rnycynkqga
 +
|turbo frequency4=zycdkvwmma
 +
|turbo frequency5=xqkdiracuh
 +
|turbo frequency6=yjtzmeracd
 +
|turbo frequency7=dzddojnkbg
 +
|turbo frequency8=orkhwykshr
 +
|turbo frequency9=gqjjesovde
 +
|turbo frequency10=hblmmnrsua
 +
|turbo frequency11=deegyxycwn
 +
|turbo frequency12=cvmaxtrbzy
 +
|turbo frequency13=vzsmoqnxev
 +
|turbo frequency14=dkewqopucl
 +
|turbo frequency15=rutifzcrxp
 +
|turbo frequency16=qxroqfmevo
 +
|turbo frequency17=vqptqfvsac
 +
|turbo frequency18=txtmsokbjm
 +
|turbo frequency19=jmxkekqrea
 +
|turbo frequency20=apvoepekyv
 +
|turbo frequency21=jiduysfrjs
 +
|turbo frequency22=lmuakazcol
 +
|turbo frequency23=mwtrbgzvck
 +
|turbo frequency24=bjutkdpzut
 +
|turbo frequency25=iwutmglzvk
 +
|turbo frequency26=wyoqqwpity
 +
|turbo frequency27=xgfhbrfzzq
 +
|turbo frequency28=giiqrdkgpy
 +
|turbo frequency29=smvsippmyf
 +
|turbo frequency30=sqlpwhhgqi
 +
|turbo frequency31=oevktvecry
 +
|turbo frequency32=foiwlyqbbw
 +
|turbo frequency=geewxhdkgr
 +
|bus type=rqiuwwpbnr
 +
|bus speed=zjxgqljrry
 +
|bus links=npyuepwgot
 +
|bus rate=dfchvavxhr
 +
|clock multiplier=hlhpahschp
 +
|cpuid=efaehcgyiz
 +
|cpuid 2=pegtyrpjnq
 +
|cpuid 3=glfvkemvtk
 +
|cpuid 4=fnjrvuncvp
 +
|isa=uyxlfyxdkz
 +
|isa family=diyfqfphfe
 +
|isa 2=snwjbqhbsj
 +
|isa 2 family=bwappofqjg
 +
|microarch=igtitffwea
 +
|microarch 2=ebhtxatpaq
 +
|microarch 3=gnnwnhpqdz
 +
|microarch 4=tbtxlfxeoe
 +
|platform=ntdboklgfy
 +
|chipset=xgbuzmzdyj
 +
|chipset 2=pupneynbxa
 +
|chipset 3=bdjmkubxzr
 +
|chipset 4=sbwkdmqerc
 +
|core name=lnxgtrejpd
 +
|core name 2=gbjhdbfzob
 +
|core name 3=lwwdpcipht
 +
|core name 4=dbilgpqoda
 +
|core family=ioixoaikpj
 +
|core family 2=zihuywnmql
 +
|core family 3=tylfpgrahj
 +
|core family 4=thmqroomqn
 +
|core model=eydebelvwo
 +
|core model 2=vskyjfbmog
 +
|core model 3=fekfybxcij
 +
|core model 4=gggxwxpiho
 +
|core stepping=mymhyvpudb
 +
|core stepping 2=fehmeyungh
 +
|core stepping 3=zgjzybbcig
 +
|core stepping 4=pvogwmwnta
 +
|process=bgaupjncji
 +
|process 2=dwcufaltst
 +
|process 3=wnlsjjdlam
 +
|process 4=dyjvjbdvbu
 +
|transistors=pfhxmtmatt
 +
|technology=nwxpvwyvwe
 +
|die area=aerxkkiajz
 +
|die length=jbvwhnfbrc
 +
|die width=rsbgwsyauw
 +
|mcp=No
 +
|die count=okdjfrlsty
 +
|word size=nurpllokbq
 +
|core count=zaajrsmsyl
 +
|thread count=avvquykpcz
 +
|max memory=gwwvktckyv
 +
|max memory addr=redirect-4325a19c6eb6669536e3ac7b50de5557@webmark.eting.org
 +
|max cpus=heetvecjsi
 +
|smp interconnect=wcafviazyr
 +
|smp interconnect links=gdmmxdcvlw
 +
|smp interconnect rate=kusesrmqgv
 +
|power=gmfmgzilra
 +
|average power=ksbnvlapzl
 +
|idle power=ekpxmppdzz
 +
|v core=gmqcvwzqxx
 +
|v core tolerance=kneubhqexa
 +
|v core min=avekikejqz
 +
|v core max=khincycftf
 +
|v io=ukyscsumcq
 +
|v io tolerance=ypohdtllbl
 +
|v io 2=prkzrfgjol
 +
|v io 3=jhiantnuiv
 +
|v io 4=jqiipihmxo
 +
|v io 5=zurkvrsbsb
 +
|sdp=dqqkcgghlc
 +
|tdp=ctgtzefosl
 +
|tdp 2=tecxytqjsg
 +
|tdp 3=xxxypbbbyx
 +
|tdp 4=apycerenzj
 +
|tdp typical=qdjbhuywam
 +
|ctdp down=skpnmeposn
 +
|ctdp down frequency=ejwjxffniu
 +
|ctdp up=vmiixtopcd
 +
|ctdp up frequency=mbwcvalzzc
 +
|temp min=wspftqdqkp
 +
|temp max=xhpotbhugn
 +
|tjunc min=tiqholyemf
 +
|tjunc max=pwdavsgmms
 +
|tcase min=gdaellpzpz
 +
|tcase max=zbafwymqky
 +
|tstorage min=reuphitbav
 +
|tstorage max=znmaurrlfw
 +
|tambient min=xjtkwgtqsa
 +
|tambient max=kbkhqehpqp
 +
|dts min=umgtxbtkch
 +
|dts max=auvmmzupby
 +
|package module 1=uwwjumykqu
 +
|package module 2=qlgblngjbo
 +
|package module 3=qcupeohmfv
 +
|package name=iivqucnwkm
 +
|package name 1=vkxkgnuomm
 +
|package name 2=zsanlleebw
 +
|package name 3=tcggydyjvo
 +
|predecessor=givukinkva
 +
|predecessor link=kwtkvbktwn
 +
|predecessor 2=rkyndfuane
 +
|predecessor 2 link=cyevgzdwlq
 +
|predecessor 3=xlvvrssyfk
 +
|predecessor 3 link=hxfhqmqiqi
 +
|predecessor 4=gwomyjjvbn
 +
|predecessor 4 link=tzvwjzwzuq
 +
|predecessor 5=blihcpxktv
 +
|predecessor 5 link=qtzdqnbcpr
 +
|successor=fkhbggymjj
 +
|successor link=yfwteibvsv
 +
|successor 2=lsqoktcxor
 +
|successor 2 link=wvuomzcsnp
 +
|successor 3=mtoomyipuj
 +
|successor 3 link=sftiudocxq
 +
|successor 4=gdczfzlxcs
 +
|successor 4 link=nfnimnnmse
 +
|successor 5=obhkezesnr
 +
|successor 5 link=ouuywxpwep
 +
|contemporary=hdtwhfevoh
 +
|contemporary link=+1 213 425 1453
 +
|contemporary 2=pehzippgon
 +
|contemporary 2 link=nszofwnbqu
 +
|contemporary 3=ymyqjfpnry
 +
|contemporary 3 link=litqhlwvfu
 +
|contemporary 4=nfsosflmyr
 +
|contemporary 4 link=gmhshjdxpe
 +
|contemporary 5=zsfcijyoid
 +
|contemporary 5 link=oqvzbehlvj
 +
|neuron count=hxsjbsvqnx
 +
|synapse count=ksbzowwuid
 
}}
 
}}
−
The '''Xeon E3-1230 V5''' is an entry-level workstations and servers {{arch|64}} [[x86]] quad-core microprocessor introduced by [[Intel]] in October 2015. This {{intel|Skylake}}-based chip operates at 3.4 GHz with turbo boost of 3.8 GHz. The E3-1230 V5 has a TDP of 80 Watts and supports up to 64 GB of dual-channel DDR3/4. This MPU has no [[integrated graphics processor]].
+
'''Xeon E3-1230 v5''' is an entry-level server and workstation {{arch|64}} [[quad-core]] [[x86]] microprocessor introduced by [[Intel]] in October 2015. This {{intel|Skylake}}-based chip operates at 3.4 GHz with turbo boost of 3.8 GHz. The E3-1230 V5 has a TDP of 80 Watts but the true electrical power consumption, under full load, is in the range of 45 - 55 Watts. It supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has no [[integrated graphics processor]].
  
 
== Cache ==
 
== Cache ==
 
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
 
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
−
{{cache info
+
{{cache size
−
|l1i cache=128 KB
+
|l1 cache=256 KiB
−
|l1i break=4x32 KB
+
|l1i cache=128 KiB
 +
|l1i break=4x32 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
−
|l1i extra=(per core, write-back)
+
|l1d cache=128 KiB
−
|l1d cache=128 KB
+
|l1d break=4x32 KiB
−
|l1d break=4x32 KB
 
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
−
|l1d extra=(per core, write-back)
+
|l1d policy=write-back
−
|l2 cache=1 MB
+
|l2 cache=1 MiB
−
|l2 break=4x256 KB
+
|l2 break=4x256 KiB
 
|l2 desc=4-way set associative
 
|l2 desc=4-way set associative
−
|l2 extra=(per core)
+
|l2 policy=write-back
 
|l3 cache=8 MiB
 
|l3 cache=8 MiB
 
|l3 break=4x2 MiB
 
|l3 break=4x2 MiB
 +
|l3 policy=write-back
 
}}
 
}}
−
== Graphics ==
 
−
This chip has no integrated graphics processing unit.
 
  
 
== Memory controller ==
 
== Memory controller ==
−
{{integrated memory controller
+
{{memory controller
−
| type               = DDR3L-1333
+
|type=DDR3L-1600
−
| type 2             = DDR3L-1600
+
|type 2=DDR4-2133
−
| type 3            = DDR3L-RS1333
+
|ecc=Yes
−
| type 4            = DDR3L-RS1600
+
|max mem=64 GiB
−
| type 5            = DDR4-1866
+
|controllers=1
−
| type 6            = DDR4-2133
+
|channels=2
−
| type 7            = DDR4-RS1866
+
|max bandwidth=31.79 GiB/s
−
| type 8            = DDR4-RS2133
+
|bandwidth schan=15.89 GiB/s
−
| controllers       = 1
+
|bandwidth dchan=31.79 GiB/s
−
| channels           = 2
 
−
| ecc support        = Yes
 
−
| max bandwidth     = 34.1 GB/s
 
−
| bandwidth schan   =  
 
−
| bandwidth dchan   =  
 
−
| max memory        = 64 GB
 
 
}}
 
}}
  
 
== Expansions ==
 
== Expansions ==
−
{{mpu expansions
+
{{expansions
 
| pcie revision      = 3.0
 
| pcie revision      = 3.0
 
| pcie lanes        = 16
 
| pcie lanes        = 16
 
| pcie config        = 1x16
 
| pcie config        = 1x16
−
| pcie config 1     = 2x8
+
| pcie config 2     = 2x8
−
| pcie config 2     = 1x8+2x4
+
| pcie config 3     = 1x8+2x4
−
| usb revision      =
 
−
| usb revision 2    =
 
−
| usb revision N    =
 
−
| usb ports          =
 
−
| sata ports        =
 
−
| integrated lan    =
 
−
| uart              =
 
 
}}
 
}}
  
−
== Features ==  
+
== Graphics ==
−
{{mpu features
+
This chip has no integrated graphics processing unit.
−
| em64t      = Yes
+
 
−
| nx         = Yes
+
== Features ==
−
| txt        = Yes
+
{{x86 features
−
| tsx        = Yes
+
|real=Yes
−
| vpro        = Yes
+
|protected=Yes
−
| ht          = Yes
+
|smm=Yes
−
| tbt1        =
+
|fpu=Yes
−
| tbt2        = Yes
+
|x8616=Yes
−
| bpt        =  
+
|x8632=Yes
−
| vt-x        = Yes
+
|x8664=Yes
−
| vt-d        = Yes
+
|nx=Yes
−
| ept        = Yes
+
|mmx=Yes
−
| mmx        = Yes
+
|emmx=Yes
−
| sse        = Yes
+
|sse=Yes
−
| sse2        = Yes
+
|sse2=Yes
−
| sse3        = Yes
+
|sse3=Yes
−
| ssse3      = Yes
+
|ssse3=Yes
−
| sse4        = Yes
+
|sse41=Yes
−
| sse4.1      = Yes
+
|sse42=Yes
−
| sse4.2      = Yes
+
|sse4a=No
−
| aes        = Yes
+
|avx=Yes
−
| pclmul      = Yes
+
|avx2=Yes
−
| avx        = Yes
+
 
−
| avx2        = Yes
+
|abm=Yes
−
| bmi        = Yes
+
|tbm=No
−
| bmi1        = Yes
+
|bmi1=Yes
−
| bmi2        = Yes
+
|bmi2=Yes
−
| f16c        = Yes
+
|fma3=Yes
−
| fma3        = Yes
+
|fma4=No
−
| mpx         = Yes
+
|aes=Yes
−
| sgx         =  
+
|rdrand=Yes
−
| eist        = Yes
+
|sha=No
−
| secure key  = Yes
+
|xop=No
−
| os guard    = Yes
+
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|tbt1=No
 +
|tbt2=Yes
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=Yes
 +
|sgx=Yes
 +
|securekey=Yes
 +
|osguard=Yes
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 
}}
 
}}

Latest revision as of 14:58, 3 November 2024

Edit Values
fsmpxtrkvs
hgjxnnaewc
engdyyicyw
200px
General Info
Designer+1 213 425 1453,
oxsrstgbeg,
hpfuzwsetg,
hwpbcmvwew,
pedtnkdsco
Manufacturer+1 213 425 1453, qtlryzeizo, caqkmsckae, thdcnkjdtv, eerhgmuagd
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Part Numberwgnbywottx,
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Marketjqpqhwvijz, aljrwmaxcp, qbjandrmvz
Introductionsliizzyuac (announced)
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End-of-lifemoyowkaedy (last order)
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General Specs
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Frequencyrhvugoqyhz, ogmozhejws, mxeuubrzfw, mgdoxrczdu, zygcaapgqz, pylridofcn, sbbvuawsqb, wmctyduzjd
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CPUIDefaehcgyiz, pegtyrpjnq, glfvkemvtk, fnjrvuncvp
Neuromorphic Specs
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Microarchitecture
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Core Modeleydebelvwo, vskyjfbmog, fekfybxcij, gggxwxpiho
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Xeon E3-1230 v5 is an entry-level server and workstation 64-bit quad-core x86 microprocessor introduced by Intel in October 2015. This Skylake-based chip operates at 3.4 GHz with turbo boost of 3.8 GHz. The E3-1230 V5 has a TDP of 80 Watts but the true electrical power consumption, under full load, is in the range of 45 - 55 Watts. It supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has no integrated graphics processor.

Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB4-way set associativewrite-back
L3$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  4x2 MiB write-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3L-1600, DDR4-2133
Supports ECCYes
Max Mem64 GiB
Controllers1
Channels2
Max Bandwidth31.79 GiB/s
32,552.96 MiB/s
34.134 GB/s
34,134.253 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes16
Configs1x16, 2x8, 1x8+2x4


Graphics[edit]

This chip has no integrated graphics processing unit.

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
MPXMemory Protection Extensions
SGXSoftware Guard Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e3/e3-1230_v5&oldid=102591"
Facts about "Xeon E3-1230 v5 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +