Difference between revisions of "intel/mcs-8/isa"

Latest revision as of 20:48, 17 September 2024

8008 ISA
Developer	Intel Datapoint Corporation
Implementation	8008
Dev model	Proprietary
Design	Von Neumann
Data word size	8 bit 1 octets 2 nibbles
Instruction word size	8 bit 1 octets
Instructions	48
Introduction	1972
Version	1
Format	Register-Memory
Endianness	Bi-endian
Registers	7
GPRs	7 (scratchpad)
ISAs • By Company • By Inst • By Data

The 8008 ISA (or MCS-8 ISA) was an instruction set architecture introduced by Intel in 1972 and was used in the 8008 and 8008-1 microprocessors.

This ISA has an 8-bit data and address bus. This architecture included seven 8-bit registers, 48 instructions, and interrupt capability.

Registers[edit]

The 8008 had seven scratchpad registers. A few of them had additional capabilities - A is used an an accumulator register. Registers H & L are high-order and low-order words of a 14-bit address.

Register	Size	Purpose
A	8 bit	Accumulator
B	8 bit	GP
C	8 bit	GP
D	8 bit	GP
E	8 bit	GP
H	8 bit	High-order word
L	8 bit	Low-order word

ISA[edit]

Data on the 8008 is always stored in an 8-bit binary integer.

Data Word

D₇ D₆ D₅ D₄ D₃ D₂ D₁ D₀

Instructions can be made of 1-3 bytes depending on operation. Multi-byte instructions must be stored in successive order in memory. Typical operations involving register-register operations such as arithmetic and logic operations only require one byte and take the following form:

1-Byte Inst

D₇ D₆ D₅ D₄ D₃ D₂ D₁ D₀

OPCode

Instructions that involve an immediate value have 2 bytes. The first byte stores the opcode and the second byte stores the 8-bit value.

2-Byte Inst

D₇ D₆ D₅ D₄ D₃ D₂ D₁ D₀

OPCode

Imm Value

Instructions involving an address (such as CALL and JUMP) require a 14-bit address. This is done via a 3-byte instruction where the first byte is the opcode, the second byte is the low-order word, and the third byte is the high-order word. Note that the 2 MSBs on the high-order word are don't cares.

3-Byte Inst

D₇ D₆ D₅ D₄ D₃ D₂ D₁ D₀

X₇ X₆ D₅ D₄ D₃ D₂ D₁ D₀

D₇ D₆ D₅ D₄ D₃ D₂ D₁ D₀

OPCode

High-Order Addrs

Low-Order Addrs

Listing[edit]

The 8008 ISA has 48 instructions broken a number of groups:

Index Register Instructions
Accumulator Group Instructions
Program Counter and Stack Control Instructions
Input/Output Instructions
Machine Instructions

In 1972, Intel introduced their first set of mnemonics for their instructions. This original set consists of three characters which meant it could easily be encoded into a lookup table. A few years later, when they released their 8080 and its instruction set, they also revamped the 8008 mnemonics to match the 8080's ones more closely. The newer mnemonics resemble a primitive version of modern x86 mnemonics. Since 8008 programs can be found using bother mnemonics, both the "old" and the "new" mnemonics are listed below. Both mnemonics results in identical binary values.

8008 ISA
Mnemonic (old)	Mnemonic (new)	Len	Opcode	Action
Index Register Instructions Load instructions do not affect any flag. The Inc and Dec instructions affect all flags except carry.
LR_dR_s	MOV R_d, R_s	1	11 DDD SSS₂	R_d = R_s
LR_dM	MOV R_d, M	1	11 DDD 111₂	R_d = Mem
LMR_s	MOV M, R_s	1	11 111 SSS₂	Mem = R_s
LR_dI	MVI R_d, Imm	2	00 DDD 110₂	R_d = Immed Value
LMI	MVI M, Imm	2	00 111 110₂	Mem = Immed Value
INR_d	INR R_d	1	00 DDD 000₂	R_d = R_d + 1 (R_d ≠ A)
DCR_d	DCR R_d	1	00 DDD 001₂	R_d = R_d - 1 (R_d ≠ A)
Accumulator Group Instructions The result of an ALU instruction affect all flags. The rotation instructions only affect the carry flag.
ADR_s	ADD R_s	1	10 000 SSS₂	A = A + R_s
ADM	ADD M	1	10 000 111₂	A = A + Mem
ADI	ADI	2	00 000 100₂	A = A + Immed Value
ACR_s	ADC R_s	1	10 001 SSS₂	A = Carry + R_s
ACM	ADC M	1	10 001 111₂	A = Carry + Mem
ACI	ACI	2	00 001 100₂	A = Carry + Immed Value
SUR_s	SUB R_s	1	10 010 SSS₂	A = A - R_s
SUM	SUB M	1	10 010 111₂	A = A - Mem
SUI	SUI	2	00 010 100₂	A = A - Immed Value
SBR_s	SBB R_s	1	10 011 SSS₂	A = A - (Carry + R_s)
SBM	SBB M	1	10 011 111₂	A = A - (Carry + Mem)
SBI	SCI	2	00 011 100₂	A = A - (Carry + Immed Value)
NDR_s	ANA R_s	1	10 100 SSS₂	A = A ∧ R_s
NDM	ANA M	1	10 100 111₂	A = A ∧ Mem
NDI	ANI	2	00 100 100₂	A = A ∧ Immed Value
XRR_s	XRA R_s	1	10 101 SSS₂	A = A ⊕ R_s
XRM	XRA M	1	10 101 111₂	A = A ⊕ Mem
XRI	XRI	2	00 101 100₂	A = A ⊕ Immed Value
ORR_s	ORA R_s	1	10 110 SSS₂	A = A ∨ R_s
ORM	ORA M	1	10 110 111₂	A = A ∨ Mem
ORI	ORI	2	00 110 100₂	A = A ∨ Immed Value
CRR_s	CMP R_s	1	10 111 SSS₂	Compare A with R_s, set flags
CRM	CMP M	1	10 111 111₂	Compare A with Mem, set flags
CRI	CPI	2	00 111 100₂	Compare A with Immed Value, set flags
RLC	RLC	1	00 000 010₂	Rotate A Left Once
RRC	RRC	1	00 001 010₂	Rotate A Right Once
RAL	RAL	1	00 010 010₂	Rotate A Left Through Carry Once
RAR	RAR	1	00 011 010₂	Rotate A Right Through Carry Once
Program Counter and Stack Control Instructions
JMP	JMP	3	01 XXX 100₂	Unconditional Jump to immed address
JFC	JNC	3	01 000 000₂	If carry = 0, jump to immed address
JFZ	JNZ	3	01 001 000₂	If result ≠ 0, jump to immed address
JFS	JP	3	01 010 000₂	If sign = 0 (positive), jump to immed address
JFP	JPO	3	01 011 000₂	If parity = 0 (odd), jump to immed address
JTC	JC	3	01 100 000₂	If carry = 1, jump to immed address
JTZ	JZ	3	01 101 000₂	If result = 0, jump to immed address
JTS	JM	3	01 110 000₂	If sign = 1 (negative), jump to immed address
JTP	JPE	3	01 111 000₂	If parity = 1 (even), jump to immed address
CAL	CALL	3	01 XXX 110₂	Save current address onto the stack and jump to immed address
CFC	CNC	3	01 000 010₂	If carry = 0, save current address and jump to immed address
CFZ	CNZ	3	01 001 010₂	If result ≠ 0, save current address and jump to immed address
CFS	CP	3	01 010 010₂	If sign = 0 (positive), save current address and jump to immed address
CFP	CPO	3	01 011 010₂	If parity = 0 (odd), save current address and jump to immed address
CTC	CC	3	01 100 010₂	If carry = 1, save current address and jump to immed address
CTZ	CZ	3	01 101 010₂	If result = 0, save current address and jump to immed address
CTS	CM	3	01 110 010₂	If sign = 1 (negative), save current address and jump to immed address
CTP	CPE	3	01 111 010₂	If parity = 1 (even), save current address and jump to immed address
RET	RET	1	00 XXX 111₂	Unconditionally return, down one stack level
RFC	RNC	1	00 000 011₂	If carry = 0, return, down one stack level
RFZ	RNZ	1	00 001 011₂	If result ≠ 0, return, down one stack level
RFS	RP	1	00 010 011₂	If sign = 0 (positive), return, down one stack level
RFP	RPO	1	00 011 011₂	If parity = 0 (odd), return, down one stack level
RTC	RC	1	00 100 011₂	If carry = 1, return, down one stack level
RTZ	RZ	1	00 101 011₂	If result = 0, return, down one stack level
RTS	RM	1	00 110 011₂	If sign = 1 (negative), return, down one stack level
RTP	RPE	1	00 111 011₂	If parity = 1 (even), return, down one stack level
RST	RST	1	00 AAA 101₂	Call the subroutine at memory AAA000 (up one stack level)
Input/Output Instructions
INP	IN	1	01 00M MM1₂	A = PORT[MMM]
OUT	OUT	1	01 RRM MM1₂	PORT[RRMMM] = A (RR ≠ 00)
Machine Instructions
HLT	HLT	1	00 000 00X₂	Enter STOPPED state; remain there until interrupted
HLT	HLT	1	11 111 111₂	Enter STOPPED state; remain there until interrupted

@@ Line 5: / Line 5: @@
 | developer 2    = Datapoint Corporation
 | implementation = 8008
-| dev model      = proprietary
+| dev model      = Proprietary
-| design         = Von Neumann architecture
+| design         = Von Neumann
 | data size      = 8 bit
 | inst size      = 8 bit
@@ Line 12: / Line 12: @@
 | introduction   = 1972
 | version        = 1
-| format         = register-register
+| format         = Register-Memory
-| endianness     = bi-endian
+| endianness     = Bi-endian
-| registers      = 0
+| registers      = 7
 | gprs           = 7
 | gprs info      = scratchpad
@@ Line 51: / Line 51: @@
 : <div style="text-align: center; width: 175px;">1-Byte Inst<div style="border: 1px solid black;">D<sub>7</sub> D<sub>6</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="width: 165;">OPCode</div></div>
-Instructions that involve an [[immediate value]] have 2 bytes. The first bite stores the opcode and the second byte stores the 8-bit value.
+Instructions that involve an [[immediate value]] have 2 bytes. The first byte stores the opcode and the second byte stores the 8-bit value.
 :<div style="text-align: center; width: 360px;"><div style="width: 350px;">2-Byte Inst</div><div style="border: 1px solid black; width: 175px; float: left;">D<sub>7</sub> D<sub>6</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="border: 1px solid black; width: 175px; float: right;">D<sub>7</sub> D<sub>6</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="width: 175px; float: left;">OPCode</div><div style="width: 175px; float: right;">Imm Value</div></div>
@@ Line 68: / Line 68: @@
 * [[#machine|Machine Instructions]]
-In 1972, Intel introduce their first set of mnemonics for their instructions. This original set consists of three characters which meant it could easily be encoded into a lookup table. A few years later, when they released their {{intel|8080}} and its instruction set, they also revamped the 8008 mnemonics to match the 8080's ones more closely. The newer mnemonics resemble a primitive version of modern x86 mnemonics. Since 8008 programs can be found using bother mnemonics, both the "old" and the "new" mnemonics are listed below. Both mnemonics results in identical binary values.
+In 1972, Intel introduced their first set of mnemonics for their instructions. This original set consists of three characters which meant it could easily be encoded into a lookup table. A few years later, when they released their {{intel|8080}} and its instruction set, they also revamped the 8008 mnemonics to match the 8080's ones more closely. The newer mnemonics resemble a primitive version of modern x86 mnemonics. Since 8008 programs can be found using bother mnemonics, both the "old" and the "new" mnemonics are listed below. Both mnemonics results in identical binary values.
 {{isa
 | title    = 8008 ISA
 | mn title = Mnemonic (old)
-| col 1    = Mnemonic (new)
+| Mnemonic (new)
+| Len
+| Opcode
+| Action
+| cols = 5
 | listing  =
-{{inst|cols=4|section=<span id="index_register">'''Index Register Instructions'''</span><br><small>Load instructions do not affect any flag. The Inc and Dec instructions affect all flags except carry.</small>}}
+{{inst|cols=5|section=<span id="index_register">'''Index Register Instructions'''</span><br><small>Load instructions do not affect any flag. The Inc and Dec instructions affect all flags except carry.</small>}}
-{{inst|mn=LR<sub>d</sub>R<sub>s</sub>   |col 1=MOV R<sub>d</sub>, R<sub>s</sub> |op={{bin|11 DDD SSS}} |act=R<sub>d</sub> = R<sub>s</sub>}}
+{{inst|mn=LR<sub>d</sub>R<sub>s</sub>   |col 1=MOV R<sub>d</sub>, R<sub>s</sub> |col 2=1 |op={{bin|11 DDD SSS}} |act=R<sub>d</sub> = R<sub>s</sub>}}
-{{inst|mn=LR<sub>d</sub>M   |col 1=MOV R<sub>d</sub>, M |op={{bin|11 DDD 111}} |act=R<sub>d</sub> = Mem}}
+{{inst|mn=LR<sub>d</sub>M   |col 1=MOV R<sub>d</sub>, M   |col 2=1 |op={{bin|11 DDD 111}} |act=R<sub>d</sub> = Mem}}
-{{inst|mn=LMR<sub>s</sub>   |col 1=MOV R<sub>s</sub>, M |op={{bin|11 111 SSS}} |act=Mem = R<sub>s</sub>}}
+{{inst|mn=LMR<sub>s</sub>   |col 1=MOV M, R<sub>s</sub>   |col 2=1 |op={{bin|11 111 SSS}} |act=Mem = R<sub>s</sub>}}
-{{inst|mn=LR<sub>d</sub>I   |col 1=MVI R<sub>d</sub>, Imm |op={{bin|00 DDD 110}} {{bin|BB BBB BBB}} |act=R<sub>d</sub> = B<sub>7</sub>...B<sub>0</sub>}}
+{{inst|mn=LR<sub>d</sub>I   |col 1=MVI R<sub>d</sub>, Imm |col 2=2 |op={{bin|00 DDD 110}} |act=R<sub>d</sub> = Immed Value}}
-{{inst|mn=LMI   |col 1=MVI M, Imm |op={{bin|00 111 110}} {{bin|BB BBB BBB}} |act=Mem = B<sub>7</sub>...B<sub>0</sub>}}
+{{inst|mn=LMI               |col 1=MVI M, Imm             |col 2=2 |op={{bin|00 111 110}} |act=Mem = Immed Value}}
-{{inst|mn=INR<sub>d</sub>   |col 1=INR R<sub>d</sub> |op={{bin|00 DDD 000}} |act=R<sub>d</sub> = R<sub>d</sub> + 1 ({{l|neq|R<sub>d</sub>|A}})}}
+{{inst|mn=INR<sub>d</sub>   |col 1=INR R<sub>d</sub>      |col 2=1 |op={{bin|00 DDD 000}} |act=R<sub>d</sub> = R<sub>d</sub> + 1 ({{l|neq|R<sub>d</sub>|A}})}}
-{{inst|mn=DCR<sub>d</sub>   |col 1=DCR R<sub>d</sub> |op={{bin|00 DDD 001}} |act=R<sub>d</sub> = R<sub>d</sub> - 1 ({{l|neq|R<sub>d</sub>|A}})}}
+{{inst|mn=DCR<sub>d</sub>   |col 1=DCR R<sub>d</sub>      |col 2=1 |op={{bin|00 DDD 001}} |act=R<sub>d</sub> = R<sub>d</sub> - 1 ({{l|neq|R<sub>d</sub>|A}})}}
-{{inst|cols=4|section=<span id="accumulator_group">'''Accumulator Group Instructions'''</span><br><small>The result of an ALU instruction affect all flags. The rotation instructions only affect the carry flag.</small>}}
+{{inst|cols=5|section=<span id="accumulator_group">'''Accumulator Group Instructions'''</span><br><small>The result of an ALU instruction affect all flags. The rotation instructions only affect the carry flag.</small>}}
+{{inst|mn=ADR<sub>s</sub> |col 1=ADD R<sub>s</sub> |col 2=1 |op={{bin|10 000 SSS}}  |act=A = A + R<sub>s</sub>}}
+{{inst|mn=ADM             |col 1=ADD M             |col 2=1 |op={{bin|10 000 111}}  |act=A = A + Mem}}
+{{inst|mn=ADI             |col 1=ADI               |col 2=2 |op={{bin|00 000 100}}  |act=A = A + Immed Value}}
+{{inst|mn=ACR<sub>s</sub> |col 1=ADC R<sub>s</sub> |col 2=1 |op={{bin|10 001 SSS}}  |act=A = Carry + R<sub>s</sub>}}
+{{inst|mn=ACM             |col 1=ADC M             |col 2=1 |op={{bin|10 001 111}}  |act=A = Carry + Mem}}
+{{inst|mn=ACI             |col 1=ACI               |col 2=2 |op={{bin|00 001 100}}  |act=A = Carry + Immed Value}}
+{{inst|mn=SUR<sub>s</sub> |col 1=SUB R<sub>s</sub> |col 2=1 |op={{bin|10 010 SSS}}  |act=A = A - R<sub>s</sub>}}
+{{inst|mn=SUM             |col 1=SUB M             |col 2=1 |op={{bin|10 010 111}}  |act=A = A - Mem}}
+{{inst|mn=SUI             |col 1=SUI               |col 2=2 |op={{bin|00 010 100}}  |act=A = A - Immed Value}}
+{{inst|mn=SBR<sub>s</sub>  |col 1=SBB R<sub>s</sub> |col 2=1 |op={{bin|10 011 SSS}}  |act=A = A - (Carry + R<sub>s</sub>)}}
+{{inst|mn=SBM             |col 1=SBB M             |col 2=1 |op={{bin|10 011 111}}  |act=A = A - (Carry + Mem)}}
+{{inst|mn=SBI             |col 1=SCI               |col 2=2 |op={{bin|00 011 100}}  |act=A = A - (Carry + Immed Value)}}
+{{inst|mn=NDR<sub>s</sub> |col 1=ANA R<sub>s</sub> |col 2=1 |op={{bin|10 100 SSS}}  |act=A = {{l|land|A|R<sub>s</sub>}}}}
+{{inst|mn=NDM             |col 1=ANA M             |col 2=1 |op={{bin|10 100 111}}  |act=A = {{l|land|A|Mem}}}}
+{{inst|mn=NDI             |col 1=ANI               |col 2=2 |op={{bin|00 100 100}}  |act=A = {{l|land|A|Immed Value}}}}
+{{inst|mn=XRR<sub>s</sub> |col 1=XRA R<sub>s</sub> |col 2=1 |op={{bin|10 101 SSS}}  |act=A = {{l|xor|A|R<sub>s</sub>}}}}
+{{inst|mn=XRM             |col 1=XRA M             |col 2=1 |op={{bin|10 101 111}}  |act=A = {{l|xor|A|Mem}}}}
+{{inst|mn=XRI             |col 1=XRI               |col 2=2 |op={{bin|00 101 100}}  |act=A = {{l|xor|A|Immed Value}}}}
+{{inst|mn=ORR<sub>s</sub> |col 1=ORA R<sub>s</sub> |col 2=1 |op={{bin|10 110 SSS}}  |act=A = {{l|lor|A|R<sub>s</sub>}}}}
+{{inst|mn=ORM             |col 1=ORA M             |col 2=1 |op={{bin|10 110 111}}  |act=A = {{l|lor|A|Mem}}}}
+{{inst|mn=ORI             |col 1=ORI               |col 2=2 |op={{bin|00 110 100}}  |act=A = {{l|lor|A|Immed Value}}}}
+{{inst|mn=CRR<sub>s</sub> |col 1=CMP R<sub>s</sub> |col 2=1 |op={{bin|10 111 SSS}}  |act=Compare A with R<sub>s</sub>, set flags}}
+{{inst|mn=CRM             |col 1=CMP M             |col 2=1 |op={{bin|10 111 111}}  |act=Compare A with Mem, set flags}}
+{{inst|mn=CRI             |col 1=CPI               |col 2=2 |op={{bin|00 111 100}}  |act=Compare A with Immed Value, set flags}}
+{{inst|mn=RLC |col 1=RLC |col 2=1 |op={{bin|00 000 010}}  |act=Rotate A Left Once}}
+{{inst|mn=RRC |col 1=RRC |col 2=1 |op={{bin|00 001 010}}  |act=Rotate A Right Once}}
+{{inst|mn=RAL |col 1=RAL |col 2=1 |op={{bin|00 010 010}}  |act=Rotate A Left Through Carry Once}}
+{{inst|mn=RAR |col 1=RAR |col 2=1 |op={{bin|00 011 010}}  |act=Rotate A Right Through Carry Once}}
-{{inst|cols=4|section=<span id="pc_and_stack">'''Program Counter and Stack Control Instructions'''</span>}}
+{{inst|cols=5|section=<span id="pc_and_stack">'''Program Counter and Stack Control Instructions'''</span>}}
+{{inst|mn=JMP |col 1=JMP  |col 2=3 |op={{bin|01 XXX 100}} |act=Unconditional Jump to immed address}}
+{{inst|mn=JFC |col 1=JNC  |col 2=3 |op={{bin|01 000 000}} |act=If carry = 0, jump to immed address}}
+{{inst|mn=JFZ |col 1=JNZ  |col 2=3 |op={{bin|01 001 000}} |act=If {{l|neq|result|0}}, jump to immed address}}
+{{inst|mn=JFS |col 1=JP   |col 2=3 |op={{bin|01 010 000}} |act=If sign = 0 (positive), jump to immed address}}
+{{inst|mn=JFP |col 1=JPO  |col 2=3 |op={{bin|01 011 000}} |act=If parity = 0 (odd), jump to immed address}}
+{{inst|mn=JTC  |col 1=JC   |col 2=3 |op={{bin|01 100 000}} |act=If carry = 1, jump to immed address}}
+{{inst|mn=JTZ  |col 1=JZ   |col 2=3 |op={{bin|01 101 000}} |act=If result = 0, jump to immed address}}
+{{inst|mn=JTS  |col 1=JM   |col 2=3 |op={{bin|01 110 000}} |act=If sign = 1 (negative), jump to immed address}}
+{{inst|mn=JTP  |col 1=JPE  |col 2=3 |op={{bin|01 111 000}} |act=If parity = 1 (even), jump to immed address}}
+{{inst|mn=CAL |col 1=CALL |col 2=3 |op={{bin|01 XXX 110}} |act=Save current address onto the stack and jump to immed address}}
+{{inst|mn=CFC |col 1=CNC  |col 2=3 |op={{bin|01 000 010}} |act=If carry = 0, save current address and jump to immed address}}
+{{inst|mn=CFZ |col 1=CNZ  |col 2=3 |op={{bin|01 001 010}} |act=If {{l|neq|result|0}}, save current address and jump to immed address}}
+{{inst|mn=CFS |col 1=CP   |col 2=3 |op={{bin|01 010 010}} |act=If sign = 0 (positive), save current address and jump to immed address}}
+{{inst|mn=CFP |col 1=CPO  |col 2=3 |op={{bin|01 011 010}} |act=If parity = 0 (odd), save current address and jump to immed address}}
+{{inst|mn=CTC  |col 1=CC   |col 2=3 |op={{bin|01 100 010}} |act=If carry = 1, save current address and jump to immed address}}
+{{inst|mn=CTZ  |col 1=CZ   |col 2=3 |op={{bin|01 101 010}} |act=If result = 0, save current address and jump to immed address}}
+{{inst|mn=CTS  |col 1=CM   |col 2=3 |op={{bin|01 110 010}} |act=If sign = 1 (negative), save current address and jump to immed address}}
+{{inst|mn=CTP  |col 1=CPE  |col 2=3 |op={{bin|01 111 010}} |act=If parity = 1 (even), save current address and jump to immed address}}
+{{inst|mn=RET |col 1=RET  |col 2=1 |op={{bin|00 XXX 111}} |act=Unconditionally return, down one stack level}}
+{{inst|mn=RFC |col 1=RNC  |col 2=1 |op={{bin|00 000 011}} |act=If carry = 0, return, down one stack level}}
+{{inst|mn=RFZ |col 1=RNZ  |col 2=1 |op={{bin|00 001 011}} |act=If {{l|neq|result|0}}, return, down one stack level}}
+{{inst|mn=RFS |col 1=RP   |col 2=1 |op={{bin|00 010 011}} |act=If sign = 0 (positive), return, down one stack level}}
+{{inst|mn=RFP |col 1=RPO  |col 2=1 |op={{bin|00 011 011}} |act=If parity = 0 (odd), return, down one stack level}}
+{{inst|mn=RTC  |col 1=RC   |col 2=1 |op={{bin|00 100 011}} |act=If carry = 1, return, down one stack level}}
+{{inst|mn=RTZ  |col 1=RZ   |col 2=1 |op={{bin|00 101 011}}  |act=If result = 0, return, down one stack level}}
+{{inst|mn=RTS  |col 1=RM   |col 2=1 |op={{bin|00 110 011}} |act=If sign = 1 (negative), return, down one stack level}}
+{{inst|mn=RTP  |col 1=RPE  |col 2=1 |op={{bin|00 111 011}} |act=If parity = 1 (even), return, down one stack level}}
+{{inst|mn=RST |col 1=RST  |col 2=1 |op={{bin|00 AAA 101}} |act=Call the subroutine at memory AAA000 (up one stack level)}}
-{{inst|cols=4|section=<span id="io">'''Input/Output Instructions'''</span>}}
+{{inst|cols=5|section=<span id="io">'''Input/Output Instructions'''</span>}}
-{{inst|cols=4|section=<span id="machine">'''Machine Instructions'''</span>}}
+{{inst|mn=INP |col 1=IN  |col 2=1 |op={{bin|01 00M MM1}}  |act=A = PORT[MMM]}}
+{{inst|mn=OUT |col 1=OUT |col 2=1 |op={{bin|01 RRM MM1}}  |act=PORT[RRMMM] = A ({{l|neq|RR|00}})}}
+{{inst|cols=5|section=<span id="machine">'''Machine Instructions'''</span>}}
+{{inst|mn=HLT |col 1=HLT |col 2=1 |op={{bin|00 000 00X}}  |act=Enter STOPPED state; remain there until interrupted}}
+{{inst|mn=HLT |col 1=HLT |col 2=1 |op={{bin|11 111 111}}  |act=Enter STOPPED state; remain there until interrupted}}
 }}

designer	Intel + and Datapoint Corporation +
first launched	1972 +
full page name	intel/mcs-8/isa +
implementation	8008 - Intel +
instance of	instruction set architecture +
instruction count	48 +
instruction word size	8 bit (1 octets) +
name	8008 +
word size	8 bit (1 octets, 2 nibbles) +

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas

Samsung

Latest revision as of 20:48, 17 September 2024

Contents

Registers[edit]

ISA[edit]

Listing[edit]

See also[edit]