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Difference between revisions of "mitsubishi/melps 4"

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| package 4        = DIP64
 
| package 4        = DIP64
 
| package 5        = QFP68
 
| package 5        = QFP68
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| package 6        = QFP72
 
}}
 
}}
−
The '''MELPS 4''' was a family of {{arch|4}} [[microcontroller]]s developed by [[Mitsubishi]] and introduce in March of 1978. Originally designed using [[pMOS]] technology, a second chip '''MELPS 41''' (and later MELPS 42) was designed using [[CMOS]] technology.
+
The '''MELPS 4''' was a family of {{arch|4}} [[microcontroller]]s developed by [[Mitsubishi]] and introduce in March of [[1978]]. Originally designed using [[pMOS]] technology, a second chip '''MELPS 41''' (and later MELPS 42) was designed using [[CMOS]] technology.
 +
 
 +
== Design ==
 +
{{empty section}}
 +
 
 +
== ISA ==
 +
{{empty section}}
  
 
== Members ==
 
== Members ==
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! colspan="7" | Family Members
 
! colspan="7" | Family Members
 
|-
 
|-
−
! Part !! ROM !! RAM !! Frequency !! I/O<br>Ports !! Package !! Notes
+
! Part !! ROM !! RAM !! Frequency !! I/O Ports !! Package !! Notes
 
|-
 
|-
−
| {{\|M58840}} || 2048x9-bit || 128x4-bit || 300 kHz - 600 kHz || 25 || DIP42 || incorporates a A/D converter
+
| {{\|M58840}} || 2048x 9-bit || 128x 4-bit || 300 kHz - 600 kHz || 25 || DIP42 || incorporates a A/D converter
 
|-
 
|-
−
| {{\|M58841}} || 2048x9-bit || 128x4-bit || 300 kHz - 600 kHz || 25 || DIP42 || Identical to {{\|M58840}}, except separate RESET (pin 20)
+
| {{\|M58841}} || 2048x 9-bit || 128x 4-bit || 300 kHz - 600 kHz || 25 || DIP42 || Identical to {{\|M58840}}, except separate RESET (pin 20)
 
|-
 
|-
−
| {{\|M58842S}} || || 128x4-bit || 300 kHz - 600 kHz || 25 || DIP64 || MELPS 4 System Evaluation Device (external ROM)
+
| {{\|M58842S}} || || 128x 4-bit || 300 kHz - 600 kHz || 25 || DIP64 || MELPS 4 System Evaluation Device (external ROM)
 
|-
 
|-
−
| {{\|M58843}} || 1024x9-bit || 64x4-bit || 300 kHz - 600 kHz || 23  || DIP28 ||
+
| {{\|M58843}} || 1024x 9-bit || 64x 4-bit || 300 kHz - 600 kHz || 23  || DIP28 ||
 
|-
 
|-
−
| {{\|M58844}} || 1024x9-bit || 64x4-bit || 300 kHz - 600 kHz || 36 || DIP40 || Same as {{\|M58843}}, more I/O
+
| {{\|M58844}} || 1024x 9-bit || 64x 4-bit || 300 kHz - 600 kHz || 36 || DIP40 || Same as {{\|M58843}}, more I/O
 
|-
 
|-
−
| {{\|M58845}} || 2048x9-bit || 128x4-bit || 300 kHz - 600 kHz || 31  || DIP42 ||
+
| {{\|M58845}} || 2048x 9-bit || 128x 4-bit || 300 kHz - 600 kHz || 31  || DIP42 ||
 
|-
 
|-
−
| {{\|M58846}} || 2048x9-bit || 128x4-bit || 300 kHz - 600 kHz || 31  || DIP42 ||
+
| {{\|M58846}} || 2048x 9-bit || 128x 4-bit || 300 kHz - 600 kHz || 31  || DIP42 ||
 
|-
 
|-
−
| {{\|M58847}} || 2048x9-bit || 128x4-bit || 240 kHz - 400 kHz || 22  || DIP40 ||
+
| {{\|M58847}} || 2048x 9-bit || 128x 4-bit || 240 kHz - 400 kHz || 22  || DIP40 ||
 
|-
 
|-
−
| {{\|M58494}} || 4096x10-bit || 32x4-bit || 100 kHz - 455 kHz || || QFP68,<br>QFP72 || "MELPS 41"
+
| {{\|M58494}} || 4096x 10-bit || 32x 4-bit || 100 kHz - 455 kHz || || QFP68, QFP72 || "MELPS 41"
 
|-
 
|-
−
| {{\|M58496}} || 2048x10-bit || 128x4-bit || 250 kHz - 525 kHz || 28 || QFP72 || "MELPS 42"
+
| {{\|M58496}} || 2048x 10-bit || 128x 4-bit || 250 kHz - 525 kHz || 28 || QFP72 || "MELPS 42"
 
|-
 
|-
−
| {{\|M58497}} || 2048x10-bit || 128x4-bit || 120 kHz - 260 kHz || 28 || QFP72 || "MELPS 42"
+
| {{\|M58497}} || 2048x 10-bit || 128x 4-bit || 120 kHz - 260 kHz || 28 || QFP72 || "MELPS 42"
 
|}
 
|}
  
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| {{\|PCA0401}} || single-board system-evaluation computer for {{\|M58840}}
 
| {{\|PCA0401}} || single-board system-evaluation computer for {{\|M58840}}
 
|}
 
|}
 +
 
== Software Support ==
 
== Software Support ==
 
{| class="wikitable sortable"
 
{| class="wikitable sortable"
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| GBISMOO02 || FORTRAN || MELPS 41 Simulator-MELCOM 70
 
| GBISMOO02 || FORTRAN || MELPS 41 Simulator-MELCOM 70
 
|-
 
|-
−
| GBISPOO03 || FORTRAN || MELPS 41 Pape~-Tape Generation Program for PROM Writers-MELCOM 70
+
| GBISPOO03 || FORTRAN || MELPS 41 Paper-Tape Generation Program for PROM Writers-MELCOM 70
 
|}
 
|}
−
== Design ==
+
 
−
{{empty section}}
 
−
== ISA ==
 
−
{{empty section}}
 
 
== Documents ==
 
== Documents ==
 
* [[:File:Mitsubishi MELPS 4 (1982).pdf|MELPS 4 (1982)]]
 
* [[:File:Mitsubishi MELPS 4 (1982).pdf|MELPS 4 (1982)]]
 
* [[:File:Mitsubishi MELPS 41-42 (1982).pdf|MELPS 41/42 (1982)]]
 
* [[:File:Mitsubishi MELPS 41-42 (1982).pdf|MELPS 41/42 (1982)]]
  
 +
== See also ==
 +
* {{mitsu|M350xx|Mitsubishi M350xx}}
 +
* {{mitsu|M50430|Mitsubishi M50430}}/{{mitsu|M50440|M50440}}
 +
* {{mitsu|M50460|Mitsubishi M50460}}/{{mitsu|M50560|M50560}}
 +
* {{mitsu|M5072|Mitsubishi M5072}}/{{mitsu|M5076|M5076}}
 +
* {{mitsu|M5090|Mitsubishi M5090}} (4-bit)
 +
 +
* {{mitsu|M37409|Mitsubishi M37409}} (8-bit)
 +
* {{mitsu|M58850|Mitsubishi M58850}} (8-bit)
  
  
 
{{stub}}
 
{{stub}}
−
{{DEFAULTSORT:MELPS 4}}
+
[[Category:mitsubishi]]
−
[[Category:Mitsubishi microprocessors]]
 
 
[[Category:4-bit microprocessors]]
 
[[Category:4-bit microprocessors]]
 
[[Category:1978 microprocessors]]
 
[[Category:1978 microprocessors]]
 
[[Category:microprocessor families]]
 
[[Category:microprocessor families]]
−
[[Category:MELPS 4 family]]
 

Latest revision as of 18:50, 15 November 2025

Mitsubishi MELPS 4
no photo (ic).svg
Developer Mitsubishi
Manufacturer Mitsubishi
Type microcontrollers
Production 1978
ISA MELPS 4
Word size 4 bit
0.5 octets
1 nibbles
Technology pMOS, CMOS
Clock 100 kHz-600 kHz
Package DIP28, DIP40, DIP42, DIP64, QFP68, QFP72

The MELPS 4 was a family of 4-bit microcontrollers developed by Mitsubishi and introduce in March of 1978. Originally designed using pMOS technology, a second chip MELPS 41 (and later MELPS 42) was designed using CMOS technology.

Design[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

ISA[edit]

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Members[edit]

Family Members
Part ROM RAM Frequency I/O Ports Package Notes
M58840 2048x 9-bit 128x 4-bit 300 kHz - 600 kHz 25 DIP42 incorporates a A/D converter
M58841 2048x 9-bit 128x 4-bit 300 kHz - 600 kHz 25 DIP42 Identical to M58840, except separate RESET (pin 20)
M58842S 128x 4-bit 300 kHz - 600 kHz 25 DIP64 MELPS 4 System Evaluation Device (external ROM)
M58843 1024x 9-bit 64x 4-bit 300 kHz - 600 kHz 23 DIP28
M58844 1024x 9-bit 64x 4-bit 300 kHz - 600 kHz 36 DIP40 Same as M58843, more I/O
M58845 2048x 9-bit 128x 4-bit 300 kHz - 600 kHz 31 DIP42
M58846 2048x 9-bit 128x 4-bit 300 kHz - 600 kHz 31 DIP42
M58847 2048x 9-bit 128x 4-bit 240 kHz - 400 kHz 22 DIP40
M58494 4096x 10-bit 32x 4-bit 100 kHz - 455 kHz QFP68, QFP72 "MELPS 41"
M58496 2048x 10-bit 128x 4-bit 250 kHz - 525 kHz 28 QFP72 "MELPS 42"
M58497 2048x 10-bit 128x 4-bit 120 kHz - 260 kHz 28 QFP72 "MELPS 42"

Others[edit]

Part Description
PCA0401 single-board system-evaluation computer for M58840

Software Support[edit]

No Language Name
GBIASOOO1 FORTRAN MELPS 4 Cross Assembler-MELCOM 70
GBIASOO02 FORTRAN MELPS 4 Cross Assembler-MELCOM 7000 or COSMO 700
GBISMOOO1 FORTRAN MELPS 4 Simulator-MELCOM 70
GBISPOOO1 FORTRAN MELPS 4 Paper-Tape Generation Program for PROM writer-MELCOM 70
GBISPOO02 FORTRAN MELPS 4 Paper-Tape Generation Program for PROM Writers-MELCOM 7000 and COSMO 700
GBIASOO03 FORTRAN MELPS 41 Cross Assembler-MELCOM 70
GBISMOO02 FORTRAN MELPS 41 Simulator-MELCOM 70
GBISPOO03 FORTRAN MELPS 41 Paper-Tape Generation Program for PROM Writers-MELCOM 70

Documents[edit]

See also[edit]


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Facts about "MELPS 4 - Mitsubishi"
RDF feed
designerMitsubishi +
full page namemitsubishi/melps 4 +
instance ofmicrocontroller family +
instruction set architectureMELPS 4 +
main designerMitsubishi +
manufacturerMitsubishi +
nameMitsubishi MELPS 4 +
packageDIP28 +, DIP40 +, DIP42 +, DIP64 +, QFP68 + and QFP72 +
technologypMOS + and CMOS +
word size4 bit (0.5 octets, 1 nibbles) +