|
|
| Line 1: |
Line 1: |
| − | {{intel title|Microarchitectures}}
| + | D |
| − | Below is a list of [[Intel]] [[microarchitectures]]:
| |
| − | == CPU Microarchitectures ==
| |
| − | <table class="wikitable sortable">
| |
| − | <tr><th colspan="12" style="background:#D6D6FF;">Intel CPU Microarchitectures</th></tr>
| |
| − | <tr><th colspan="3">General</th><th colspan="5">Details</th></tr>
| |
| − | <tr><th>µarch</th><th>Introduction</th><th>Phase-out</th><th>[[technology node|Process]]</th><th>Cores</th><th colspan="3">Pipeline</th></tr>
| |
| − | {{#ask:
| |
| − | [[Category:cpu microarchitectures by intel]]
| |
| − | [[instance of::microarchitecture]]
| |
| − | [[designer::Intel]]
| |
| − | |?full page name
| |
| − | |?name
| |
| − | |?first launched
| |
| − | |?phase-out
| |
| − | |?process
| |
| − | |?core count
| |
| − | |?pipeline stages
| |
| − | |?pipeline stages (min)
| |
| − | |?pipeline stages (max)
| |
| − | |sort=first launched
| |
| − | |order=ascending
| |
| − | |format=template
| |
| − | |template=proc table 2
| |
| − | |userparam=9
| |
| − | |valuesep=,
| |
| − | |mainlabel=-
| |
| − | }}
| |
| − | </table>
| |
| − | | |
| − | == GPU Microarchitectures ==
| |
| − | <table class="wikitable sortable">
| |
| − | <tr><th colspan="12" style="background:#D6D6FF;">Intel GPU Microarchitectures</th></tr>
| |
| − | <tr><th colspan="3">General</th><th colspan="5">Details</th></tr>
| |
| − | <tr><th>µarch</th><th>Introduction</th><th>Phase-out</th><th>[[technology node|Process]]</th></tr>
| |
| − | {{#ask:
| |
| − | [[Category:gpu microarchitectures by intel]]
| |
| − | [[instance of::microarchitecture]]
| |
| − | [[designer::Intel]]
| |
| − | |?full page name
| |
| − | |?name
| |
| − | |?first launched
| |
| − | |?phase-out
| |
| − | |?process
| |
| − | |sort=first launched
| |
| − | |order=ascending
| |
| − | |format=template
| |
| − | |template=proc table 2
| |
| − | |userparam=5
| |
| − | |valuesep=,
| |
| − | |mainlabel=-
| |
| − | }}
| |
| − | </table>
| |
| − | | |
| − | == Many-core ==
| |
| − | {{work-in-progress}}
| |
| − | | |
| − | === Initial effort & Polaris ===
| |
| − | Intel actual large effort research into the area of [[many-core]] started after the February 2004 [[Intel Developer Forum]] following Pradeep Dubey famous keynote titled "The Era of Tera." Around the [[2004]]-[[2005]] Intel formed a number of strategic research projects to explorer and study the feasibility and challenges of many-core and tera-scale processing. One of the earliest examples of such project was the {{intel|Tera-scale Computing Research Program}} which was unveiled by Justin Rattner, then-CTO, at the spring 2006 Intel Develop Forum.
| |
| − | | |
| − | The first product to come directly from that project was {{intel|Polaris|l=arch}}, an 80-core chip designed using modular tiles that could scale in the x- and y- directions using a routing system that interconnected all the tiles in a [[mesh topology]]. Fabricated on a [[65 nm process]], the chip was around 275 mm² and incorporated around 100M transistors. The chip also attempted to solve some of the inherent problems dealing with a large amount of cores such as the bandwidth. [[3D IC|3D]] [[stacked]] SRAM was utilized to achieve bandwidths of over 1 Tb/s. Operating as high as 5.7 GHz, the chip could reach over 1.8 [[teraFLOPS]] of sustained performance.
| |
| − | | |
| − | === Larrabee ===
| |
| − | {{empty section}}
| |
