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| developer 2    = Datapoint Corporation
 
| developer 2    = Datapoint Corporation
 
| implementation = 8008
 
| implementation = 8008
−
| dev model      = proprietary
+
| dev model      = Proprietary
−
| design        = Von Neumann architecture
+
| design        = Von Neumann
 
| data size      = 8 bit
 
| data size      = 8 bit
 
| inst size      = 8 bit
 
| inst size      = 8 bit
Line 12: Line 12:
 
| introduction  = 1972
 
| introduction  = 1972
 
| version        = 1
 
| version        = 1
−
| format        = register-register
+
| format        = Register-Memory
−
| endianness    = bi-endian
+
| endianness    = Bi-endian
−
| registers      = 0
+
| registers      = 7
 
| gprs          = 7
 
| gprs          = 7
 
| gprs info      = scratchpad
 
| gprs info      = scratchpad
 
}}
 
}}
−
The '''8008 ISA''' (or ''MCS-8 ISA'') was an instruction set architecture used in the {{intel|mcs-8/8008|8008}} and {{intel|mcs-8/8008-1|8008-1}} microprocessors.
+
The '''8008 ISA''' (or ''MCS-8 ISA'') was an instruction set architecture introduced by [[Intel]] in 1972 and was used in the {{intel|mcs-8/8008|8008}} and {{intel|mcs-8/8008-1|8008-1}} microprocessors.
  
 
This ISA has an {{arch|8}} data and address bus. This architecture included seven 8-bit registers, 48 instructions, and interrupt capability.
 
This ISA has an {{arch|8}} data and address bus. This architecture included seven 8-bit registers, 48 instructions, and interrupt capability.
Line 45: Line 45:
 
== ISA ==
 
== ISA ==
 
Data on the 8008 is always stored in an 8-bit binary integer.
 
Data on the 8008 is always stored in an 8-bit binary integer.
−
: <div style="text-align: center; width: 150px;">Data Word<div style="border: 1px solid black;">D<sub>7</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div></div>
+
: <div style="text-align: center; width: 175px;">Data Word<div style="border: 1px solid black;">D<sub>7</sub> D<sub>6</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div></div>
  
 
Instructions can be made of 1-3 bytes depending on operation. Multi-byte instructions must be stored in successive order in memory. Typical operations involving register-register operations such as arithmetic and logic operations only require one byte and take the following form:
 
Instructions can be made of 1-3 bytes depending on operation. Multi-byte instructions must be stored in successive order in memory. Typical operations involving register-register operations such as arithmetic and logic operations only require one byte and take the following form:
  
−
: <div style="text-align: center; width: 150px;">1-Byte Inst<div style="border: 1px solid black;">D<sub>7</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="width: 140px;">OPCode</div></div>
+
: <div style="text-align: center; width: 175px;">1-Byte Inst<div style="border: 1px solid black;">D<sub>7</sub> D<sub>6</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="width: 165;">OPCode</div></div>
  
 
Instructions that involve an [[immediate value]] have 2 bytes. The first bite stores the opcode and the second byte stores the 8-bit value.
 
Instructions that involve an [[immediate value]] have 2 bytes. The first bite stores the opcode and the second byte stores the 8-bit value.
  
−
:<div style="text-align: center; width: 310px;"><div style="width: 300px;">2-Byte Inst</div><div style="border: 1px solid black; width: 150px; float: left;">D<sub>7</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="border: 1px solid black; width: 150px; float: right;">D<sub>7</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="width: 150px; float: left;">OPCode</div><div style="width: 150px; float: right;">Imm Value</div></div>
+
:<div style="text-align: center; width: 360px;"><div style="width: 350px;">2-Byte Inst</div><div style="border: 1px solid black; width: 175px; float: left;">D<sub>7</sub> D<sub>6</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="border: 1px solid black; width: 175px; float: right;">D<sub>7</sub> D<sub>6</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="width: 175px; float: left;">OPCode</div><div style="width: 175px; float: right;">Imm Value</div></div>
  
 
Instructions involving an address (such as CALL and JUMP) require a 14-bit address. This is done via a 3-byte instruction where the first byte is the opcode, the second byte is the low-order word, and the third byte is the high-order word. Note that the 2 MSBs on the high-order word are [[don't care]]s.
 
Instructions involving an address (such as CALL and JUMP) require a 14-bit address. This is done via a 3-byte instruction where the first byte is the opcode, the second byte is the low-order word, and the third byte is the high-order word. Note that the 2 MSBs on the high-order word are [[don't care]]s.
  
−
:<div style="text-align: center; width: 470px;"><div style="width: 470px;">3-Byte Inst</div><div style="border: 1px solid black; width: 150px; float: left;">D<sub>7</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="border: 1px solid black; width: 150px; float: right;">D<sub>7</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="border: 1px solid black; width: 150px; margin:0 auto;width:150px;">D<sub>7</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="width: 150px; float: left;">OPCode</div><div style="width: 150px; float: right;">High-Order Add</div><div style="width: 150px; margin:0 auto;">Low-Order Add</div></div>
+
:<div style="text-align: center; width: 550px;"><div style="width: 525px;">3-Byte Inst</div><div style="border: 1px solid black; width: 175px; float: left;">D<sub>7</sub> D<sub>6</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="border: 1px solid black; width: 175px; float: right;">{{X}}<sub>7</sub> {{X}}<sub>6</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="border: 1px solid black; width: 175px; margin:0 auto;width:175px;">D<sub>7</sub> D<sub>6</sub> D<sub>5</sub> D<sub>4</sub> D<sub>3</sub> D<sub>2</sub> D<sub>1</sub> D<sub>0</sub></div><div style="width: 175px; float: left;">OPCode</div><div style="width: 175px; float: right;">High-Order Addrs</div><div style="width: 175px; margin:0 auto;">Low-Order Addrs</div></div>
 +
 
 +
=== Listing ===
 +
The 8008 ISA has 48 instructions broken a number of groups:
 +
 
 +
* [[#index_register|Index Register Instructions]]
 +
* [[#accumulator_group|Accumulator Group Instructions]]
 +
* [[#pc_and_stack|Program Counter and Stack Control Instructions]]
 +
* [[#io|Input/Output Instructions]]
 +
* [[#machine|Machine Instructions]]
 +
 
 +
In 1972, Intel introduced their first set of mnemonics for their instructions. This original set consists of three characters which meant it could easily be encoded into a lookup table. A few years later, when they released their {{intel|8080}} and its instruction set, they also revamped the 8008 mnemonics to match the 8080's ones more closely. The newer mnemonics resemble a primitive version of modern x86 mnemonics. Since 8008 programs can be found using bother mnemonics, both the "old" and the "new" mnemonics are listed below. Both mnemonics results in identical binary values.
 +
 
 +
{{isa
 +
| title    = 8008 ISA
 +
| mn title = Mnemonic (old)
 +
| Mnemonic (new)
 +
| Len
 +
| Opcode
 +
| Action
 +
| cols = 5
 +
| listing  =
 +
 
 +
{{inst|cols=5|section=<span id="index_register">'''Index Register Instructions'''</span><br><small>Load instructions do not affect any flag. The Inc and Dec instructions affect all flags except carry.</small>}}
 +
{{inst|mn=LR<sub>d</sub>R<sub>s</sub>  |col 1=MOV R<sub>d</sub>, R<sub>s</sub> |col 2=1 |op={{bin|11 DDD SSS}} |act=R<sub>d</sub> = R<sub>s</sub>}}
 +
{{inst|mn=LR<sub>d</sub>M  |col 1=MOV R<sub>d</sub>, M  |col 2=1 |op={{bin|11 DDD 111}} |act=R<sub>d</sub> = Mem}}
 +
{{inst|mn=LMR<sub>s</sub>  |col 1=MOV M, R<sub>s</sub>  |col 2=1 |op={{bin|11 111 SSS}} |act=Mem = R<sub>s</sub>}}
 +
{{inst|mn=LR<sub>d</sub>I  |col 1=MVI R<sub>d</sub>, Imm |col 2=2 |op={{bin|00 DDD 110}} |act=R<sub>d</sub> = Immed Value}}
 +
{{inst|mn=LMI              |col 1=MVI M, Imm            |col 2=2 |op={{bin|00 111 110}} |act=Mem = Immed Value}}
 +
{{inst|mn=INR<sub>d</sub>  |col 1=INR R<sub>d</sub>      |col 2=1 |op={{bin|00 DDD 000}} |act=R<sub>d</sub> = R<sub>d</sub> + 1 ({{l|neq|R<sub>d</sub>|A}})}}
 +
{{inst|mn=DCR<sub>d</sub>  |col 1=DCR R<sub>d</sub>      |col 2=1 |op={{bin|00 DDD 001}} |act=R<sub>d</sub> = R<sub>d</sub> - 1 ({{l|neq|R<sub>d</sub>|A}})}}
 +
 
 +
{{inst|cols=5|section=<span id="accumulator_group">'''Accumulator Group Instructions'''</span><br><small>The result of an ALU instruction affect all flags. The rotation instructions only affect the carry flag.</small>}}
 +
{{inst|mn=ADR<sub>s</sub> |col 1=ADD R<sub>s</sub> |col 2=1 |op={{bin|10 000 SSS}}  |act=A = A + R<sub>s</sub>}}
 +
{{inst|mn=ADM            |col 1=ADD M            |col 2=1 |op={{bin|10 000 111}}  |act=A = A + Mem}}
 +
{{inst|mn=ADI            |col 1=ADI              |col 2=2 |op={{bin|00 000 100}}  |act=A = A + Immed Value}}
 +
{{inst|mn=ACR<sub>s</sub> |col 1=ADC R<sub>s</sub> |col 2=1 |op={{bin|10 001 SSS}}  |act=A = Carry + R<sub>s</sub>}}
 +
{{inst|mn=ACM            |col 1=ADC M            |col 2=1 |op={{bin|10 001 111}}  |act=A = Carry + Mem}}
 +
{{inst|mn=ACI            |col 1=ACI              |col 2=2 |op={{bin|00 001 100}}  |act=A = Carry + Immed Value}}
 +
{{inst|mn=SUR<sub>s</sub> |col 1=SUB R<sub>s</sub> |col 2=1 |op={{bin|10 010 SSS}}  |act=A = A - R<sub>s</sub>}}
 +
{{inst|mn=SUM            |col 1=SUB M            |col 2=1 |op={{bin|10 010 111}}  |act=A = A - Mem}}
 +
{{inst|mn=SUI            |col 1=SUI              |col 2=2 |op={{bin|00 010 100}}  |act=A = A - Immed Value}}
 +
{{inst|mn=SBR<sub>s</sub>  |col 1=SBB R<sub>s</sub> |col 2=1 |op={{bin|10 011 SSS}}  |act=A = A - (Carry + R<sub>s</sub>)}}
 +
{{inst|mn=SBM            |col 1=SBB M            |col 2=1 |op={{bin|10 011 111}}  |act=A = A - (Carry + Mem)}}
 +
{{inst|mn=SBI            |col 1=SCI              |col 2=2 |op={{bin|00 011 100}}  |act=A = A - (Carry + Immed Value)}}
 +
{{inst|mn=NDR<sub>s</sub> |col 1=ANA R<sub>s</sub> |col 2=1 |op={{bin|10 100 SSS}}  |act=A = {{l|land|A|R<sub>s</sub>}}}}
 +
{{inst|mn=NDM            |col 1=ANA M            |col 2=1 |op={{bin|10 100 111}}  |act=A = {{l|land|A|Mem}}}}
 +
{{inst|mn=NDI            |col 1=ANI              |col 2=2 |op={{bin|00 100 100}}  |act=A = {{l|land|A|Immed Value}}}}
 +
{{inst|mn=XRR<sub>s</sub> |col 1=XRA R<sub>s</sub> |col 2=1 |op={{bin|10 101 SSS}}  |act=A = {{l|xor|A|R<sub>s</sub>}}}}
 +
{{inst|mn=XRM            |col 1=XRA M            |col 2=1 |op={{bin|10 101 111}}  |act=A = {{l|xor|A|Mem}}}}
 +
{{inst|mn=XRI            |col 1=XRI              |col 2=2 |op={{bin|00 101 100}}  |act=A = {{l|xor|A|Immed Value}}}}
 +
{{inst|mn=ORR<sub>s</sub> |col 1=ORA R<sub>s</sub> |col 2=1 |op={{bin|10 110 SSS}}  |act=A = {{l|lor|A|R<sub>s</sub>}}}}
 +
{{inst|mn=ORM            |col 1=ORA M            |col 2=1 |op={{bin|10 110 111}}  |act=A = {{l|lor|A|Mem}}}}
 +
{{inst|mn=ORI            |col 1=ORI              |col 2=2 |op={{bin|00 110 100}}  |act=A = {{l|lor|A|Immed Value}}}}
 +
{{inst|mn=CRR<sub>s</sub> |col 1=CMP R<sub>s</sub> |col 2=1 |op={{bin|10 111 SSS}}  |act=Compare A with R<sub>s</sub>, set flags}}
 +
{{inst|mn=CRM            |col 1=CMP M            |col 2=1 |op={{bin|10 111 111}}  |act=Compare A with Mem, set flags}}
 +
{{inst|mn=CRI            |col 1=CPI              |col 2=2 |op={{bin|00 111 100}}  |act=Compare A with Immed Value, set flags}}
 +
{{inst|mn=RLC |col 1=RLC |col 2=1 |op={{bin|00 000 010}}  |act=Rotate A Left Once}}
 +
{{inst|mn=RRC |col 1=RRC |col 2=1 |op={{bin|00 001 010}}  |act=Rotate A Right Once}}
 +
{{inst|mn=RAL |col 1=RAL |col 2=1 |op={{bin|00 010 010}}  |act=Rotate A Left Through Carry Once}}
 +
{{inst|mn=RAR |col 1=RAR |col 2=1 |op={{bin|00 011 010}}  |act=Rotate A Right Through Carry Once}}
 +
 
 +
{{inst|cols=5|section=<span id="pc_and_stack">'''Program Counter and Stack Control Instructions'''</span>}}
 +
{{inst|mn=JMP |col 1=JMP  |col 2=3 |op={{bin|01 XXX 100}} |act=Unconditional Jump to immed address}}
 +
{{inst|mn=JFC |col 1=JNC  |col 2=3 |op={{bin|01 000 000}} |act=If carry = 0, jump to immed address}}
 +
{{inst|mn=JFZ |col 1=JNZ  |col 2=3 |op={{bin|01 001 000}} |act=If {{l|neq|result|0}}, jump to immed address}}
 +
{{inst|mn=JFS |col 1=JP  |col 2=3 |op={{bin|01 010 000}} |act=If sign = 0 (positive), jump to immed address}}
 +
{{inst|mn=JFP |col 1=JPO  |col 2=3 |op={{bin|01 011 000}} |act=If parity = 0 (odd), jump to immed address}}
 +
{{inst|mn=JTC  |col 1=JC  |col 2=3 |op={{bin|01 100 000}} |act=If carry = 1, jump to immed address}}
 +
{{inst|mn=JTZ  |col 1=JZ  |col 2=3 |op={{bin|01 101 000}} |act=If result = 0, jump to immed address}}
 +
{{inst|mn=JTS  |col 1=JM  |col 2=3 |op={{bin|01 110 000}} |act=If sign = 1 (negative), jump to immed address}}
 +
{{inst|mn=JTP  |col 1=JPE  |col 2=3 |op={{bin|01 111 000}} |act=If parity = 1 (even), jump to immed address}}
 +
{{inst|mn=CAL |col 1=CALL |col 2=3 |op={{bin|01 XXX 110}} |act=Save current address onto the stack and jump to immed address}}
 +
{{inst|mn=CFC |col 1=CNC  |col 2=3 |op={{bin|01 000 010}} |act=If carry = 0, save current address and jump to immed address}}
 +
{{inst|mn=CFZ |col 1=CNZ  |col 2=3 |op={{bin|01 001 010}} |act=If {{l|neq|result|0}}, save current address and jump to immed address}}
 +
{{inst|mn=CFS |col 1=CP  |col 2=3 |op={{bin|01 010 010}} |act=If sign = 0 (positive), save current address and jump to immed address}}
 +
{{inst|mn=CFP |col 1=CPO  |col 2=3 |op={{bin|01 011 010}} |act=If parity = 0 (odd), save current address and jump to immed address}}
 +
{{inst|mn=CTC  |col 1=CC  |col 2=3 |op={{bin|01 100 010}} |act=If carry = 1, save current address and jump to immed address}}
 +
{{inst|mn=CTZ  |col 1=CZ  |col 2=3 |op={{bin|01 101 010}} |act=If result = 0, save current address and jump to immed address}}
 +
{{inst|mn=CTS  |col 1=CM  |col 2=3 |op={{bin|01 110 010}} |act=If sign = 1 (negative), save current address and jump to immed address}}
 +
{{inst|mn=CTP  |col 1=CPE  |col 2=3 |op={{bin|01 111 010}} |act=If parity = 1 (even), save current address and jump to immed address}}
 +
{{inst|mn=RET |col 1=RET  |col 2=1 |op={{bin|00 XXX 111}} |act=Unconditionally return, down one stack level}}
 +
{{inst|mn=RFC |col 1=RNC  |col 2=1 |op={{bin|00 000 011}} |act=If carry = 0, return, down one stack level}}
 +
{{inst|mn=RFZ |col 1=RNZ  |col 2=1 |op={{bin|00 001 011}} |act=If {{l|neq|result|0}}, return, down one stack level}}
 +
{{inst|mn=RFS |col 1=RP  |col 2=1 |op={{bin|00 010 011}} |act=If sign = 0 (positive), return, down one stack level}}
 +
{{inst|mn=RFP |col 1=RPO  |col 2=1 |op={{bin|00 011 011}} |act=If parity = 0 (odd), return, down one stack level}}
 +
{{inst|mn=RTC  |col 1=RC  |col 2=1 |op={{bin|00 100 011}} |act=If carry = 1, return, down one stack level}}
 +
{{inst|mn=RTZ  |col 1=RZ  |col 2=1 |op={{bin|00 101 011}}  |act=If result = 0, return, down one stack level}}
 +
{{inst|mn=RTS  |col 1=RM  |col 2=1 |op={{bin|00 110 011}} |act=If sign = 1 (negative), return, down one stack level}}
 +
{{inst|mn=RTP  |col 1=RPE  |col 2=1 |op={{bin|00 111 011}} |act=If parity = 1 (even), return, down one stack level}}
 +
{{inst|mn=RST |col 1=RST  |col 2=1 |op={{bin|00 AAA 101}} |act=Call the subroutine at memory AAA000 (up one stack level)}}
 +
 
 +
{{inst|cols=5|section=<span id="io">'''Input/Output Instructions'''</span>}}
 +
{{inst|mn=INP |col 1=IN  |col 2=1 |op={{bin|01 00M MM1}}  |act=A = PORT[MMM]}}
 +
{{inst|mn=OUT |col 1=OUT |col 2=1 |op={{bin|01 RRM MM1}}  |act=PORT[RRMMM] = A ({{l|neq|RR|00}})}}
 +
 
 +
{{inst|cols=5|section=<span id="machine">'''Machine Instructions'''</span>}}
 +
{{inst|mn=HLT |col 1=HLT |col 2=1 |op={{bin|00 000 00X}}  |act=Enter STOPPED state; remain there until interrupted}}
 +
{{inst|mn=HLT |col 1=HLT |col 2=1 |op={{bin|11 111 111}}  |act=Enter STOPPED state; remain there until interrupted}}
 +
}}
  
 
== See also ==
 
== See also ==
 
* {{intel|MCS-8}}
 
* {{intel|MCS-8}}
 
* {{intel|MCS-4}}
 
* {{intel|MCS-4}}

Latest revision as of 09:11, 29 September 2019

8008 ISA
Developer Intel
Datapoint Corporation
Implementation 8008
Dev model Proprietary
Design Von Neumann
Data word size 8 bit
1 octets
2 nibbles
Instruction word size 8 bit
1 octets
Instructions 48
Introduction 1972
Version 1
Format Register-Memory
Endianness Bi-endian
Registers 7
GPRs 7 (scratchpad)
ISAs • By Company • By Inst • By Data

The 8008 ISA (or MCS-8 ISA) was an instruction set architecture introduced by Intel in 1972 and was used in the 8008 and 8008-1 microprocessors.

This ISA has an 8-bit data and address bus. This architecture included seven 8-bit registers, 48 instructions, and interrupt capability.

Registers[edit]

The 8008 had seven scratchpad registers. A few of them had additional capabilities - A is used an an accumulator register. Registers H & L are high-order and low-order words of a 14-bit address.

Register Size Purpose
A 8 bit Accumulator
B 8 bit GP
C 8 bit GP
D 8 bit GP
E 8 bit GP
H 8 bit High-order word
L 8 bit Low-order word

ISA[edit]

Data on the 8008 is always stored in an 8-bit binary integer.

Data Word
D7 D6 D5 D4 D3 D2 D1 D0

Instructions can be made of 1-3 bytes depending on operation. Multi-byte instructions must be stored in successive order in memory. Typical operations involving register-register operations such as arithmetic and logic operations only require one byte and take the following form:

1-Byte Inst
D7 D6 D5 D4 D3 D2 D1 D0
OPCode

Instructions that involve an immediate value have 2 bytes. The first bite stores the opcode and the second byte stores the 8-bit value.

2-Byte Inst
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
OPCode
Imm Value

Instructions involving an address (such as CALL and JUMP) require a 14-bit address. This is done via a 3-byte instruction where the first byte is the opcode, the second byte is the low-order word, and the third byte is the high-order word. Note that the 2 MSBs on the high-order word are don't cares.

3-Byte Inst
D7 D6 D5 D4 D3 D2 D1 D0
X7 X6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
OPCode
High-Order Addrs
Low-Order Addrs

Listing[edit]

The 8008 ISA has 48 instructions broken a number of groups:

In 1972, Intel introduced their first set of mnemonics for their instructions. This original set consists of three characters which meant it could easily be encoded into a lookup table. A few years later, when they released their 8080 and its instruction set, they also revamped the 8008 mnemonics to match the 8080's ones more closely. The newer mnemonics resemble a primitive version of modern x86 mnemonics. Since 8008 programs can be found using bother mnemonics, both the "old" and the "new" mnemonics are listed below. Both mnemonics results in identical binary values.

8008 ISA
Mnemonic (old) Mnemonic (new) Len Opcode Action
Index Register Instructions
Load instructions do not affect any flag. The Inc and Dec instructions affect all flags except carry.
LRdRsMOV Rd, Rs111 DDD SSS2Rd = Rs
LRdMMOV Rd, M111 DDD 1112Rd = Mem
LMRsMOV M, Rs111 111 SSS2Mem = Rs
LRdIMVI Rd, Imm200 DDD 1102Rd = Immed Value
LMIMVI M, Imm200 111 1102Mem = Immed Value
INRdINR Rd100 DDD 0002Rd = Rd + 1 (Rd ≠ A)
DCRdDCR Rd100 DDD 0012Rd = Rd - 1 (Rd ≠ A)
Accumulator Group Instructions
The result of an ALU instruction affect all flags. The rotation instructions only affect the carry flag.
ADRsADD Rs110 000 SSS2A = A + Rs
ADMADD M110 000 1112A = A + Mem
ADIADI200 000 1002A = A + Immed Value
ACRsADC Rs110 001 SSS2A = Carry + Rs
ACMADC M110 001 1112A = Carry + Mem
ACIACI200 001 1002A = Carry + Immed Value
SURsSUB Rs110 010 SSS2A = A - Rs
SUMSUB M110 010 1112A = A - Mem
SUISUI200 010 1002A = A - Immed Value
SBRsSBB Rs110 011 SSS2A = A - (Carry + Rs)
SBMSBB M110 011 1112A = A - (Carry + Mem)
SBISCI200 011 1002A = A - (Carry + Immed Value)
NDRsANA Rs110 100 SSS2A = A ∧ Rs
NDMANA M110 100 1112A = A ∧ Mem
NDIANI200 100 1002A = A ∧ Immed Value
XRRsXRA Rs110 101 SSS2A = A ⊕ Rs
XRMXRA M110 101 1112A = A ⊕ Mem
XRIXRI200 101 1002A = A ⊕ Immed Value
ORRsORA Rs110 110 SSS2A = A ∨ Rs
ORMORA M110 110 1112A = A ∨ Mem
ORIORI200 110 1002A = A ∨ Immed Value
CRRsCMP Rs110 111 SSS2Compare A with Rs, set flags
CRMCMP M110 111 1112Compare A with Mem, set flags
CRICPI200 111 1002Compare A with Immed Value, set flags
RLCRLC100 000 0102Rotate A Left Once
RRCRRC100 001 0102Rotate A Right Once
RALRAL100 010 0102Rotate A Left Through Carry Once
RARRAR100 011 0102Rotate A Right Through Carry Once
Program Counter and Stack Control Instructions
JMPJMP301 XXX 1002Unconditional Jump to immed address
JFCJNC301 000 0002If carry = 0, jump to immed address
JFZJNZ301 001 0002If result ≠ 0, jump to immed address
JFSJP301 010 0002If sign = 0 (positive), jump to immed address
JFPJPO301 011 0002If parity = 0 (odd), jump to immed address
JTCJC301 100 0002If carry = 1, jump to immed address
JTZJZ301 101 0002If result = 0, jump to immed address
JTSJM301 110 0002If sign = 1 (negative), jump to immed address
JTPJPE301 111 0002If parity = 1 (even), jump to immed address
CALCALL301 XXX 1102Save current address onto the stack and jump to immed address
CFCCNC301 000 0102If carry = 0, save current address and jump to immed address
CFZCNZ301 001 0102If result ≠ 0, save current address and jump to immed address
CFSCP301 010 0102If sign = 0 (positive), save current address and jump to immed address
CFPCPO301 011 0102If parity = 0 (odd), save current address and jump to immed address
CTCCC301 100 0102If carry = 1, save current address and jump to immed address
CTZCZ301 101 0102If result = 0, save current address and jump to immed address
CTSCM301 110 0102If sign = 1 (negative), save current address and jump to immed address
CTPCPE301 111 0102If parity = 1 (even), save current address and jump to immed address
RETRET100 XXX 1112Unconditionally return, down one stack level
RFCRNC100 000 0112If carry = 0, return, down one stack level
RFZRNZ100 001 0112If result ≠ 0, return, down one stack level
RFSRP100 010 0112If sign = 0 (positive), return, down one stack level
RFPRPO100 011 0112If parity = 0 (odd), return, down one stack level
RTCRC100 100 0112If carry = 1, return, down one stack level
RTZRZ100 101 0112If result = 0, return, down one stack level
RTSRM100 110 0112If sign = 1 (negative), return, down one stack level
RTPRPE100 111 0112If parity = 1 (even), return, down one stack level
RSTRST100 AAA 1012Call the subroutine at memory AAA000 (up one stack level)
Input/Output Instructions
INPIN101 00M MM12A = PORT[MMM]
OUTOUT101 RRM MM12PORT[RRMMM] = A (RR ≠ 00)
Machine Instructions
HLTHLT100 000 00X2Enter STOPPED state; remain there until interrupted
HLTHLT111 111 1112Enter STOPPED state; remain there until interrupted

See also[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/mcs-8/isa&oldid=93709"
Facts about "8008 ISA - Intel"
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designerIntel + and Datapoint Corporation +
first launched1972 +
full page nameintel/mcs-8/isa +
implementation8008 - Intel +
instance ofinstruction set architecture +
instruction count48 +
instruction word size8 bit (1 octets) +
name8008 +
word size8 bit (1 octets, 2 nibbles) +