Semiconductor & Computer Engineering
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Difference between revisions of "36-bit architecture"
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{{Architecture sizes}} | {{Architecture sizes}} | ||
| − | The '''36-bit [[architecture]]''' is a [[microprocessor]] or [[computer]] architecture that has a [[datapath]] width or a highest [[operand]] width of 36 bits | + | The '''36-bit [[architecture]]''' is a [[microprocessor]] or [[computer]] architecture that has a [[datapath]] width or a highest [[operand]] width of 36 bits . These architectures typically have a matching [[register file]] with [[registers]] width of 36 bits. 36-bit systems allowed for the manipulation of 6 [[6-bit character]]s. |
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== 36-bit systems == | == 36-bit systems == | ||
| + | * {{decc|PDP-3}} | ||
* {{decc|PDP-6}} | * {{decc|PDP-6}} | ||
* {{decc|PDP-10}} | * {{decc|PDP-10}} | ||
Latest revision as of 06:19, 27 June 2018
The 36-bit architecture is a microprocessor or computer architecture that has a datapath width or a highest operand width of 36 bits . These architectures typically have a matching register file with registers width of 36 bits. 36-bit systems allowed for the manipulation of 6 6-bit characters.
36-bit systems[edit]
- PDP-3
- PDP-6
- PDP-10
- GE GE-600
- Honeywell 6000
- IBM 700
- IBM 7000
- MIT TX-2
- Symbolics 3600
- UNIVAC 1100
- UNIVAC 2200
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