Semiconductor & Computer Engineering
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Difference between revisions of "university of manchester/spinnaker"
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|market=Server | |market=Server | ||
|first launched=20th May, 2011 | |first launched=20th May, 2011 | ||
| − | |frequency= | + | |frequency=200MHz |
|isa=ARMv9 | |isa=ARMv9 | ||
|isa family=ARM | |isa family=ARM | ||
|microarch=ARM968 | |microarch=ARM968 | ||
| − | |die area= | + | |die area=102mm² |
| − | |die length=10. | + | |die length=10.386mm |
| − | |die width=9. | + | |die width=9.786mm |
|mcp=Yes | |mcp=Yes | ||
|die count=2 | |die count=2 | ||
|core count=18 | |core count=18 | ||
|max cpus=1,036,800 (system) | |max cpus=1,036,800 (system) | ||
| − | |max memory= | + | |max memory=128MB (chip), 7TB (system) |
| − | |power= | + | |power=1W (chip), 90kW (system) |
|neuron count=1,000,000,000 | |neuron count=1,000,000,000 | ||
}} | }} | ||
| + | |||
| + | {{title|SpiNNaker}} | ||
| + | |||
| + | Project SpiNNaker (an abbreviation for "[[spiking neural network]] (SNN) architecture") is a research project by the APT - Advanced Processor Technologies Research Group of the University of Manchester. In its full configuration, the system consists of 1,036,800 ARM9 cores that are capable of simulating up to one billion neurons in real time. | ||
| + | |||
| + | |||
| + | == Overview == | ||
| + | The SpiNNaker engine is using the ''SpiNNaker multicore System-On-Chip (SoC)'' as single nodes. Each chip contains two dies: The first die holds 18 ARM968 cores, 32kB SRAM, 64kB data tightly coupled memory (DTCM) per core, 32kB instruction tightly coupled memory (ITCM) per core, an Ethernet interface and a ''custom interconnect fabric''. The second die within the SoC holds 128MB of shared SDRAM. | ||
| + | |||
| + | == System Components == | ||
| + | |||
| + | === ARM968 === | ||
| + | |||
| + | === Vectored [[Interrupt]] Controller (VIC) === | ||
| + | |||
| + | === Counter/Timer units === | ||
| + | |||
| + | === Ethernet === | ||
| + | |||
| + | === DMA === | ||
| + | |||
| + | === Memory === | ||
| + | |||
| + | |||
| + | |||
| + | == Routing fabric == | ||
| + | |||
Revision as of 14:01, 18 May 2018
| Edit Values | |
| SpiNNaker multicore SoC | |
| General Info | |
| Designer | APT Advanced Processor Technologies Research Group |
| Market | Server |
| Introduction | 20th May, 2011 (launched) |
| General Specs | |
| Frequency | 200MHz |
| Neuromorphic Specs | |
| Neurons | 1,000,000,000 |
| Microarchitecture | |
| ISA | ARMv9 (ARM) |
| Microarchitecture | ARM968 |
| Die | 102mm² 10.386mm × 9.786mm |
| MCP | Yes (2 dies) |
| Cores | 18 |
| Max Memory | 128MB (chip), 7TB (system) |
| Multiprocessing | |
| Max SMP | 1,036,800 (system)-Way (Multiprocessor) |
| Electrical | |
| Power dissipation | 1W (chip), 90kW (system) |
Project SpiNNaker (an abbreviation for "spiking neural network (SNN) architecture") is a research project by the APT - Advanced Processor Technologies Research Group of the University of Manchester. In its full configuration, the system consists of 1,036,800 ARM9 cores that are capable of simulating up to one billion neurons in real time.
Contents
Overview
The SpiNNaker engine is using the SpiNNaker multicore System-On-Chip (SoC) as single nodes. Each chip contains two dies: The first die holds 18 ARM968 cores, 32kB SRAM, 64kB data tightly coupled memory (DTCM) per core, 32kB instruction tightly coupled memory (ITCM) per core, an Ethernet interface and a custom interconnect fabric. The second die within the SoC holds 128MB of shared SDRAM.
System Components
ARM968
Vectored Interrupt Controller (VIC)
Counter/Timer units
Ethernet
DMA
Memory
Routing fabric
References
- Furber et al. "Overview of the SpiNNaker System Architecture" IEEE Transactions On Computers, Vol. 62, No. 12, December 2013
Facts about "SpiNNaker - APT - The University of Manchester"
| base frequency | 200 MHz (0.2 GHz, 200,000 kHz) + |
| core count | 18 + |
| designer | APT Advanced Processor Technologies Research Group + |
| die area | 102 mm² (0.158 in², 1.02 cm², 102,000,000 µm²) + |
| die count | 2 + |
| die length | 10.386 mm (1.039 cm, 0.409 in, 10,386 µm) + |
| die width | 9.786 mm (0.979 cm, 0.385 in, 9,786 µm) + |
| first launched | May 20, 2011 + |
| full page name | university of manchester/spinnaker + |
| instance of | neuromorphic chip + |
| is multi-chip package | true + |
| isa | ARMv9 + |
| isa family | ARM + |
| ldate | May 20, 2011 + |
| market segment | Server + |
| microarchitecture | ARM968 + |
| name | SpiNNaker multicore SoC + |
| neuron count | 1,000,000,000 + |
| smp max ways | 1,036,800 (system) + |