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Latest revision as of 15:27, 13 December 2017

Edit Values
Xeon E5-1607 v4
General Info
DesignerIntel
ManufacturerIntel
Model NumberE5-1607 v4
Part NumberCM8066002395500
S-SpecSR2PH
QKFB (QS), QKFC (QS)
MarketServer
IntroductionJune 20, 2016 (announced)
June 20, 2016 (launched)
ShopAmazon
General Specs
FamilyXeon E5
SeriesE5-1000
LockedYes
Frequency3,100 MHz
Bus typeDMI 2.0
Bus rate5 GT/s
Clock multiplier38
CPUID406F1
Microarchitecture
MicroarchitectureBroadwell
PlatformGrantley EP Workstation
ChipsetC610 Series
Core NameBroadwell EP
Core Family6
Core Model4F
Core SteppingR0
Process14 nm
Transistors3,200,000,000
TechnologyCMOS
Die246.24 mm²
Word Size64 bit
Cores4
Threads4
Max Memory1,536 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore1.82 V
VI/O1.2 V ± 3%
TDP140 W
Tcase0 °C – 69 °C
Tstorage-25 °C – 125 °C

The Xeon E5-1607 v4 is a 64-bit quad-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for 1S workstations. Operating at 3.1 GHz with no turbo boost support, this MPU has a TDP of 140 W and is manufactured on a 14 nm process (based on Broadwell). This model has no hyper-threading support.

This specific model appears to be only OEM for Lenovo and HP.

Cache[edit]

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core, write-back)
L1D$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core, write-back)
L2$ 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
4x256 KiB 8-way set associative (per core, write-back)
L3$ 10 MiB
10,240 KiB
10,485,760 B
0.00977 GiB
4x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics[edit]

This microprocessor has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR4-2133
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 63.58 GiB/s
Bandwidth (single) 15.89 GiB/s
Bandwidth (dual) 31.79 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes40
Configsx4, x16


Features[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-1607_v4&oldid=70972"
Facts about "Xeon E5-1607 v4 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon E5-1607 v4 - Intel#io +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel vpro technologytrue +
has second level address translation supporttrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description20-way set associative +
l3$ size10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) +
max pcie lanes40 +