From WikiChip
Difference between revisions of "cavium/octeon/cn3830-600bg1521-nsp"
< cavium‎ | octeon

m (Bot: moving all {{mpu}} to {{chip}})
 
(4 intermediate revisions by 2 users not shown)
Line 1: Line 1:
 
{{cavium title|CN3830-600 NSP}}
 
{{cavium title|CN3830-600 NSP}}
−
{{mpu
+
{{chip
 
| name                = Cavium CN3830-600 NSP
 
| name                = Cavium CN3830-600 NSP
 
| no image            =  
 
| no image            =  
Line 10: Line 10:
 
| model number        = CN3830-600 NSP
 
| model number        = CN3830-600 NSP
 
| part number        = CN3830-600BG1521-NSP
 
| part number        = CN3830-600BG1521-NSP
−
| part number 1      =
 
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| market              = Networking
 
| market              = Networking
 
| first announced    = September 13, 2004  
 
| first announced    = September 13, 2004  
Line 78: Line 78:
 
| tambient max        =  
 
| tambient max        =  
  
−
| packaging          = Yes
+
|package module 1={{packages/cavium/fcbga-1521}}
−
| package 0          = BGA-1521
 
−
| package 0 type      = BGA
 
−
| package 0 pins      = 1521
 
−
| package 0 pitch    =
 
−
| package 0 width    =
 
−
| package 0 length    =
 
−
| package 0 height    =
 
−
| socket 0            =
 
−
| socket 0 type      =
 
 
}}
 
}}
 
The '''CN3830-600 NSP''' is a {{arch|64}} [[quad-core]] [[MIPS]] network service [[microprocessor]] (NSP) designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates four {{cavium|cnMIPS|l=arch}} cores, operates at 600 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
 
The '''CN3830-600 NSP''' is a {{arch|64}} [[quad-core]] [[MIPS]] network service [[microprocessor]] (NSP) designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates four {{cavium|cnMIPS|l=arch}} cores, operates at 600 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
 +
 +
== Cache ==
 +
{{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}}
 +
{{cache size
 +
|l1 cache=160 KiB
 +
|l1i cache=128 KiB
 +
|l1i break=4x32 KiB
 +
|l1i desc=64-way set associative
 +
|l1d cache=32 KiB
 +
|l1d break=4x8 KiB
 +
|l1d desc=64-way set associative
 +
|l1d policy=Write-through
 +
|l2 cache=1 MiB
 +
|l2 break=1x1 MiB
 +
|l2 desc=8-way set associative
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR2-800
 +
|ecc=Yes
 +
|max mem=16 GiB
 +
|controllers=1
 +
|channels=1
 +
|width=128 bit
 +
|max bandwidth=11.92 GiB/s
 +
|bandwidth schan=11.92 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
|pcix width=64 bit
 +
|pcix clock=133.33 MHz
 +
|pcix rate=1,017.25 MiB/s
 +
|pcix extra=host or slave
 +
|uart=yes
 +
|uart ports=2
 +
|gp io=Yes
 +
}}
 +
 +
== Networking ==
 +
{{network
 +
|mii opts=Yes
 +
|rgmii=yes
 +
|rgmii ports=8
 +
|spi opts=Yes
 +
|spi42=Yes
 +
|spi42 ports=2
 +
}}
 +
 +
== Hardware Accelerators ==
 +
{{accelerators
 +
|encryption=Yes
 +
|encryption type=DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH
 +
|regex=Yes
 +
|regex feature=16 Engines
 +
|compression=Yes
 +
|decompression=Yes
 +
|tcp=Yes
 +
|qos=Yes
 +
}}
 +
 +
== Block diagram ==
 +
[[File:octeon cn38xx block diagram.png|750px]]
 +
 +
== Datasheet ==
 +
* [[:File:octeon cn38xx and cn36xx product brief.pdf|OCTEON CN38XX/CN36XX 4 to 16-Core Product Brief]]

Latest revision as of 15:11, 13 December 2017

Edit Values
Cavium CN3830-600 NSP
octeon cn38xx.png
General Info
DesignerCavium
ManufacturerTSMC
Model NumberCN3830-600 NSP
Part NumberCN3830-600BG1521-NSP
MarketNetworking
IntroductionSeptember 13, 2004 (announced)
June 1, 2005 (launched)
General Specs
FamilyOCTEON
SeriesCN3800
Frequency600 MHz
Microarchitecture
ISAMIPS64 (MIPS)
MicroarchitecturecnMIPS
Core NamecnMIPS
Process130 nm
TechnologyCMOS
Word Size64 bit
Cores4
Threads4
Max Memory16 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Packaging
PackageFCBGA-1521 (BGA)
Ball Count1521
InterconnectBGA-1521

The CN3830-600 NSP is a 64-bit quad-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2005. This processor, which incorporates four cnMIPS cores, operates at 600 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.

Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$160 KiB
163,840 B
0.156 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB64-way set associative 
L1D$32 KiB
32,768 B
0.0313 MiB
4x8 KiB64-way set associativeWrite-through
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  1x1 MiB8-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-800
Supports ECCYes
Max Mem16 GiB
Controllers1
Channels1
Width128 bit
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 11.92 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI-X
Width64 bit
Clock133.33 MHz
Rate1,017.25 MiB/s
Featureshost or slave
UART
Ports2
GP I/OYes


Networking[edit]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
RGMIIYes (Ports: 8)
SPI
SPI-4.2Yes (Ports: 2)

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
Encryption
Hardware ImplementationYes
TypesDES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH
RegEx
RegExYes
Features16 Engines
Networking
TCPYes
QoSYes
Compression
CompressionYes
DecompressionYes

Block diagram[edit]

octeon cn38xx block diagram.png

Datasheet[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon/cn3830-600bg1521-nsp&oldid=70222"
Facts about "CN3830-600 NSP - Cavium"
RDF feed
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for regular expressiontrue +
has hardware accelerators for tcp packet processingtrue +
l1$ size160 KiB (163,840 B, 0.156 MiB) +
l1d$ description64-way set associative +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description64-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
supported memory typeDDR2-800 +