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Difference between revisions of "intel/xeon e5/e5-2699 v4"
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| pcie revision      = 3.0
 
| pcie lanes        = 40
 
| pcie lanes        = 40

Revision as of 14:55, 13 December 2017

Template:mpu The Xeon E5-2699 v4 is a 64-bit docosa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for segment-optimized 2S environments (2U Square form factors). Operating at 2.2 GHz with a turbo boost frequency of 3.6 GHz for a single active core, this MPU has a TDP of 145 W and is manufactured on a 14 nm process (based on Broadwell).

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 704 KiB
720,896 B
0.688 MiB
22x32 KiB 8-way set associative (per core, write-back)
L1D$ 704 KiB
720,896 B
0.688 MiB
22x32 KiB 8-way set associative (per core, write-back)
L2$ 5.5 MiB
5,632 KiB
5,767,168 B
0.00537 GiB
22x256 KiB 8-way set associative (per core, write-back)
L3$ 55 MiB
56,320 KiB
57,671,680 B
0.0537 GiB
22x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics

This microprocessor has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR4-2400
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 71.53 GiB/s
Bandwidth (single) 17.88 GiB/s
Bandwidth (dual) 35.76 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes40
Configsx4, x16


Features

Benchmarks

[Edit Benchmarks]

Test: SPEC CPU2017
Tested: 2016-10-16 23:43:00-0400
Chips: 2, Cores: 44, Threads: 44
benchmarks.svg
Vendor: HPE
System: ProLiant ML350 Gen9 (2.20 GHz, Intel Xeon E5-2699 v4)
SPECspeed2017_fp_base: 6.16
SPECspeed2017_fp_peak: 7.61
Test: SPEC CPU2017
Tested: 2016-12-09 02:21:01-0500
Chips: 2, Cores: 44, Threads: 44
benchmarks.svg
Vendor: HPE
System: ProLiant ML350 Gen9 (2.20 GHz, Intel Xeon E5-2699 v4)
SPECspeed2017_int_base: 5.8
SPECspeed2017_int_peak: 6.43
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-2699_v4&oldid=69926"
Facts about "Xeon E5-2699 v4 - Intel"
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"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon E5-2699 v4 - Intel#io +, Xeon E5-2699 v4 - Intel + and Xeon E5-2699 v4 - Intel +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1d$ description8-way set associative +
l1d$ size704 KiB (720,896 B, 0.688 MiB) +
l1i$ description8-way set associative +
l1i$ size704 KiB (720,896 B, 0.688 MiB) +
l2$ description8-way set associative +
l2$ size5.5 MiB (5,632 KiB, 5,767,168 B, 0.00537 GiB) +
l3$ description20-way set associative +
l3$ size55 MiB (56,320 KiB, 57,671,680 B, 0.0537 GiB) +
max pcie lanes40 +