From WikiChip
Difference between revisions of "intel/core i7/i7-5500du"
< intel‎ | core i7

m (Bot: Automated text replacement (-\| electrical += Yes +))
m (Bot: replacing deprecated (and now obselete) {{mpu features}} with {{x86 features}})
Line 144: Line 144:
  
 
== Features ==
 
== Features ==
{{mpu features
+
{{x86 features
 
| em64t      = Yes
 
| em64t      = Yes
 
| nx          = Yes
 
| nx          = Yes

Revision as of 14:46, 13 December 2017

Template:mpu Core i7-5500DU is a 64-bit dual-core x86 performance mobile microprocessor introduced by Intel in early 2016. This processor operates at 2.4 GHz and is based on the Broadwell microarchitecture manufactured on a 14 nm process.

Cache

Main article: Skylake § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB 8-way set associative (per core, write-back)
L1D$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB 8-way set associative (per core, write-back)
L2$ 512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
2x256 KiB 4-way set associative (per core, write-back)
L3$ 4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
2x2 MiB 16-way set associative (shared)

Graphics

No information about the integrated graphics processor is available.

Memory controller

Integrated Memory Controller
Type DDR3L-1866, LPDDR4-2133
Controllers 1
Channels 2
ECC Support Yes
Max bandwidth 31.79 GiB/s
Bandwidth (single) 15.89 GiB/s
Bandwidth (dual) 31.79 GiB/s
Max memory 32 GiB

Expansions

Template:mpu expansions

Features

has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Extended Page Tables +, Memory Protection Extensions + and Software Guard Extensions +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ description16-way set associative +
l3$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
x86/has memory protection extensionstrue +
x86/has software guard extensionstrue +