Revision as of 13:42, 10 September 2017

Template:mpu Helio P23 is a mid-range performance 64-bit octa-core ARM LTE system on a chip designed by MediaTek set to launch in late 2017. This SoC, which is fabricated on TSMC's 16 nm process, incorporates eight Cortex-A53 cores with four little cores operating at up to 1.65 GHz and four big cores operating at up to 2.3 GHz. The Helio P23 supports up to 6 GiB of dual-channel LPDDR4X-3200 memory and incorporates a modem supporting LTE User Equipment (UE) category 6 and 7 (DL)/13 (UL).

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Cortex-A53 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

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Memory controller

The Helio P23 supports either: up to 4 GiB of single-channel 32-bit LPDDR3-1866, or up to 6 GiB of dual-channel 16 bit LPDDR4X-3200 memory.

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type LPDDR4X-3200, LPDDR3-1866 Supports ECC No Max Mem 6 GiB Controllers 1 Channels 2 Width 16 bit, 32 bit Max Bandwidth 11.92 GiB/s 12,206.08 MiB/s 12.799 GB/s 12,799.003 MB/s 0.0116 TiB/s 0.0128 TB/s Bandwidth Single 5.96 GiB/s Double 11.92 GiB/s