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Difference between revisions of "mediatek/helio/mt6757"
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(→‎Utilizing devices)
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|market 2=Embedded
 
|market 2=Embedded
 
|first announced=September 22, 2016
 
|first announced=September 22, 2016
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|first launched=2017
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|first launched=November, 2016
 
|family=Helio
 
|family=Helio
 
|series=Helio P
 
|series=Helio P
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|max memory=6 GiB
 
|max memory=6 GiB
 
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'''Helio P20''' ('''MT6757''') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and set to be launched in [[2017]]. This SoC, which incorporates eight {{armh|Cortex-A53|l=arch}} cores and is manufactured on [[TSMC]]'s [[16 nm process]], operates at up to 2.3 GHz and supports  up to 6 GiB of dual-channel LPDDR4X-3200 memory. This chip incorporates the {{imgtec|Mali-T880}} [[IGP]] operating at 900  MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) category 6.
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'''Helio P20''' ('''MT6757''') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and set to be launched late [[2016]]. This SoC, which incorporates eight {{armh|Cortex-A53|l=arch}} cores and is manufactured on [[TSMC]]'s [[16 nm process]], operates at up to 2.3 GHz and supports  up to 6 GiB of dual-channel LPDDR4X-3200 memory. This chip incorporates the {{imgtec|Mali-T880}} [[IGP]] operating at 900  MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) category 6.
  
 
== Cache ==
 
== Cache ==

Revision as of 14:42, 24 July 2017

Template:mpu Helio P20 (MT6757) is a 64-bit octa-core ARM LTE system on a chip designed by MediaTek and set to be launched late 2016. This SoC, which incorporates eight Cortex-A53 cores and is manufactured on TSMC's 16 nm process, operates at up to 2.3 GHz and supports up to 6 GiB of dual-channel LPDDR4X-3200 memory. This chip incorporates the Mali-T880 IGP operating at 900 MHz. This SoC has a modem supporting LTE User Equipment (UE) category 6.

Cache

Main article: Cortex-A53 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB2-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB4-way set associative 
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  2x1 MiB16-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-3200
Supports ECCNo
Max Mem6 GiB
Controllers1
Channels2
Width32 bit
Max Bandwidth23.84 GiB/s
24,412.16 MiB/s
25.598 GB/s
25,598.005 MB/s
0.0233 TiB/s
0.0256 TB/s
Bandwidth
Single 11.92 GiB/s
Double 23.84 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
USB
Revision2.0, 3.0
Ports8
UART
GP I/OYes


Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUMali-T880
DesignerARM Holdings
Execution Units2Max Displays2
Frequency900 MHz
0.9 GHz
900,000 KHz
OutputDSI
Max Resolution
DSI1920x1080
Standards
Direct3D11.2
OpenGL3.2
OpenCL1.2
OpenGL ES3.2
OpenVG1.1
Vulkan1.0

Wireless

Antu network-wireless-connected-100.svgWireless Communications
Cellular
2G
CSD Yes
GSM Yes
GPRS Yes
EDGE Yes
3G
UMTS
TD-SCDMAYes
DC-HSDPAYes
HSUPAYes
4G
LTE Advanced
E-UTRANYes
UE Cat6

Image

New text document.svg This section is empty; you can help add the missing info by editing this page.

Video

New text document.svg This section is empty; you can help add the missing info by editing this page.

Audio

New text document.svg This section is empty; you can help add the missing info by editing this page.

Utilizing devices

  • Alcatel Idol 5S
  • Elephone P20
  • Elephone Z1
  • InnJoo Pro 2
  • Meizu E2
  • Meizu X
  • Sony Xperia XA1
  • Sony Xperia XA1
  • Sony Xperia XA1 Ultra
  • UMiDIGI S
  • UMiDIGI Z1
  • UMi Plus Extreme

This list is incomplete; you can help by expanding it.

Retrieved from "https://en.wikichip.org/w/index.php?title=mediatek/helio/mt6757&oldid=56292"
Facts about "Helio P20 (MT6757) - MediaTek"
RDF feed
has 2g supporttrue +
has 3g supporttrue +
has 4g supporttrue +
has csd supporttrue +
has dc-hsdpa supporttrue +
has e-utran supporttrue +
has ecc memory supportfalse +
has edge supporttrue +
has gprs supporttrue +
has gsm supporttrue +
has hsupa supporttrue +
has lte advanced supporttrue +
has td-scdma supporttrue +
has umts supporttrue +
integrated gpuMali-T880 +
integrated gpu base frequency900 MHz (0.9 GHz, 900,000 KHz) +
integrated gpu designerARM Holdings +
integrated gpu execution units2 +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description4-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description2-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description16-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
max memory bandwidth23.84 GiB/s (24,412.16 MiB/s, 25.598 GB/s, 25,598.005 MB/s, 0.0233 TiB/s, 0.0256 TB/s) +
max memory channels2 +
supported memory typeLPDDR4X-3200 +
used byAlcatel Idol 5S +, Elephone P20 +, Elephone Z1 +, InnJoo Pro 2 +, Meizu E2 +, Meizu X +, Sony Xperia XA1 +, Sony Xperia XA1 Ultra +, UMiDIGI S +, UMiDIGI Z1 + and UMi Plus Extreme +
user equipment category6 +