From WikiChip
Difference between revisions of "renesas/r-car/h3"
< renesas‎ | r-car

Line 25: Line 25:
 
|technology=CMOS
 
|technology=CMOS
 
|word size=64 bit
 
|word size=64 bit
−
|core count=9
+
|core count=10
−
|thread count=9
+
|thread count=10
 
|max cpus=1
 
|max cpus=1
 
|v core=0.8 V
 
|v core=0.8 V
Line 32: Line 32:
 
|package module 1={{packages/renesas/fcbga-1384}}
 
|package module 1={{packages/renesas/fcbga-1384}}
 
}}
 
}}
−
'''R-Car H3''' is a {{arch|64}} [[nona-core]] [[ARM]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2016. The H3 incorporates four {{armh|Cortex-A57}} cores, four {{armh|Cortex-A53}} cores, and a single {{armh|Cortex-R7}} core for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory. This chip incorporates the [[imagination technologies|Imagination]]'s {{imgtec|PowerVR GX6650}} [[GPU]].
+
'''R-Car H3''' is a {{arch|64}} [[deca-core]] [[ARM]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2016. The H3 incorporates four {{armh|Cortex-A57}} cores, four {{armh|Cortex-A53}} cores, and two {{armh|Cortex-R7}} cores for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory. This chip incorporates the [[imagination technologies|Imagination]]'s {{imgtec|PowerVR GX6650}} [[GPU]].
  
 
Samples for the H3 were available starting December 2015 with Renesas expecting mass production to begin in March 2018 and reach a volume of 100,000 units per month in March 2019.
 
Samples for the H3 were available starting December 2015 with Renesas expecting mass production to begin in March 2018 and reach a volume of 100,000 units per month in March 2019.
Line 39: Line 39:
 
{{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a57#Memory_Hierarchy|l1=Cortex-A53 § Cache|l2=Cortex-A57 § Cache}}
 
{{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a57#Memory_Hierarchy|l1=Cortex-A53 § Cache|l2=Cortex-A57 § Cache}}
 
{{cache size
 
{{cache size
−
|l1 cache=640 KiB
+
|l1 cache=704 KiB
−
|l1i cache=352 KiB
+
|l1i cache=384 KiB
−
|l1i break=4x48+5x32 KiB
+
|l1i break=4x48+6x32 KiB
−
|l1d cache=288 KiB
+
|l1d cache=320 KiB
−
|l1d break=9x32 KiB
+
|l1d break=10x32 KiB
 
|l2 cache=2.5 MiB
 
|l2 cache=2.5 MiB
 
}}
 
}}

Revision as of 05:55, 23 July 2017

Template:mpu R-Car H3 is a 64-bit deca-core ARM SoC designed by Renesas for the automotive industry and introduced in 2016. The H3 incorporates four Cortex-A57 cores, four Cortex-A53 cores, and two Cortex-R7 cores for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory. This chip incorporates the Imagination's PowerVR GX6650 GPU.

Samples for the H3 were available starting December 2015 with Renesas expecting mass production to begin in March 2018 and reach a volume of 100,000 units per month in March 2019.

Cache

Main articles: Cortex-A53 § Cache and Cortex-A57 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$704 KiB
720,896 B
0.688 MiB
L1I$384 KiB
393,216 B
0.375 MiB
4x48+6x32 KiB  
L1D$320 KiB
327,680 B
0.313 MiB
10x32 KiB  
L2$2.5 MiB
2,560 KiB
2,621,440 B
0.00244 GiB
     

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4-3200
Supports ECCNo
Controllers1
Channels4
Width32 bit
Max Bandwidth47.68 GiB/s
48,824.32 MiB/s
51.196 GB/s
51,196.01 MB/s
0.0466 TiB/s
0.0512 TB/s
Bandwidth
Single 11.92 GiB/s
Double 23.84 GiB/s
Quad 47.68 GiB/s

Expansions

  • PCI Express2.0 (1 lane) x 2 ch
  • USB 3.0 Host interface (DRD) × 1 ports (wPHY)
  • USB 2.0 Host/Function/OTG interface × 2 ports (wPHY)
  • SD Host interface × 4 ch (SDR104)
  • Multimedia card interface × 2 ch
  • Serial ATA interface × 1 ch
  • Media local bus (MLB) Interface × 1 ch (3 pin interface)
  • Controller Area Network (CAN-FD support) Interface × 2ch
  • Ethernet AVB 1.0-compatible MAC built in Interface: RGMII / Ethernet AVB (802.1BA)
  • SYS-DMAC x 48 ch, Realtime-DMAC x 16 ch,
  • Audio-DMAC x 32 ch, Audio(peripheral)-DMAC x 29 ch
  • 32bit timer x 26 ch
  • PWM timer × 7 ch
  • I2C bus interface × 7 ch
  • Serial communication interface (SCIF) × 11 ch
  • Quad serial peripheral interface (QSPI) x 2 ch (for boot, HyperFlash support)
  • Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
  • Ethernet controller (IEEE802.3u, RMII, without PHY)
  • Digital radio interface (DRIF) × 4 ch

Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR GX6650
DesignerImagination Technologies

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
VFPv4Vector Floating Point (VFP) v4 Extension
NEONAdvanced SIMD extension
TrustZoneTrustZone Security Extensions

Block Diagram

r-car h3 block.png
Retrieved from "https://en.wikichip.org/w/index.php?title=renesas/r-car/h3&oldid=56145"
Facts about "R-Car H3 - Renesas"
RDF feed
has ecc memory supportfalse +
integrated gpuPowerVR GX6650 +
integrated gpu designerImagination Technologies +
l1$ size704 KiB (720,896 B, 0.688 MiB) +
l1d$ size320 KiB (327,680 B, 0.313 MiB) +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ size2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) +
max memory bandwidth47.68 GiB/s (48,824.32 MiB/s, 51.196 GB/s, 51,196.01 MB/s, 0.0466 TiB/s, 0.0512 TB/s) +
max memory channels4 +
supported memory typeLPDDR4-3200 +