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Difference between revisions of "renesas/r-car/v2h"
< renesas‎ | r-car

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|max bandwidth=5.96 GiB/s
 
|max bandwidth=5.96 GiB/s
 
|bandwidth schan=5.96 GiB/s
 
|bandwidth schan=5.96 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
* Flash ROM and SRAM Data bus width: 8/16 bit
 +
* CAN 2 channels
 +
* Ethernet AVB; 1000 Mbps, 100 Mbps, IEEE802.3 PHY
 +
 +
== Graphics ==
 +
{{integrated graphics
 +
| gpu                = PowerVR SGX531
 +
| designer            = Imagination Technologies
 +
}}
 +
 +
== Features ==
 +
{{arm features
 +
|thumb=No
 +
|thumb2=No
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|thumbee=No
 +
|vfpv1=No
 +
|vfpv2=No
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|vfpv3=No
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|vfpv3-d16=No
 +
|vfpv3-f16=No
 +
|vfpv4=Yes
 +
|vfpv4-d16=No
 +
|vfpv5=No
 +
|neon=Yes
 +
|trustzone=Yes
 +
|jazelle=No
 +
|wmmx=No
 +
|wmmx2=No
 
}}
 
}}

Revision as of 05:04, 23 July 2017

Template:mpu R-Car V2H is high-performance embedded 64-bit dual-core arm SoC designed by Renesas for the automotive industry and introduced in 2014. The V2H has two Cortex-A15 cores operating at 1 GHz and incorporates the Imagination PowerVR SGX531 GPU. This SoC supports up to DDR3-1600 memory.

Cache

Main article: Cortex-A15 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB  
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB  
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
     

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1600
Supports ECCYes
Controllers1
Channels1
Width32 bit
Max Bandwidth5.96 GiB/s
6,103.04 MiB/s
6.4 GB/s
6,399.501 MB/s
0.00582 TiB/s
0.0064 TB/s
Bandwidth
Single 5.96 GiB/s

Expansions

  • Flash ROM and SRAM Data bus width: 8/16 bit
  • CAN 2 channels
  • Ethernet AVB; 1000 Mbps, 100 Mbps, IEEE802.3 PHY

Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR SGX531
DesignerImagination Technologies

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
VFPv4Vector Floating Point (VFP) v4 Extension
NEONAdvanced SIMD extension
TrustZoneTrustZone Security Extensions
Retrieved from "https://en.wikichip.org/w/index.php?title=renesas/r-car/v2h&oldid=56126"
Facts about "R-Car V2H - Renesas"
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has ecc memory supporttrue +
integrated gpuPowerVR SGX531 +
integrated gpu designerImagination Technologies +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
max memory bandwidth5.96 GiB/s (6,103.04 MiB/s, 6.4 GB/s, 6,399.501 MB/s, 0.00582 TiB/s, 0.0064 TB/s) +
max memory channels1 +
supported memory typeDDR3-1600 +