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Difference between revisions of "renesas/r-car/h3"
< renesas‎ | r-car

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|package module 1={{packages/renesas/fcbga-1384}}
 
|package module 1={{packages/renesas/fcbga-1384}}
 
}}
 
}}
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'''R-Car H3''' is a {{arch|64}} [[nona-core]] [[ARM]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2016. The H3 incorporates four {{armh|Cortex-A57}} cores, four {{armh|Cortex-A53}} cores, and a single {{armh|Cortex-R7}} core for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory.
+
'''R-Car H3''' is a {{arch|64}} [[nona-core]] [[ARM]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2016. The H3 incorporates four {{armh|Cortex-A57}} cores, four {{armh|Cortex-A53}} cores, and a single {{armh|Cortex-R7}} core for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory. This chip incorporates the [[imagination technologies|Imagination]]'s {{imgtec|PowerVR GX6650}} [[GPU]].
  
 
== Cache ==
 
== Cache ==
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|l2 cache=2.5 MiB
 
|l2 cache=2.5 MiB
 
}}
 
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=LPDDR4-3200
 +
|ecc=No
 +
|controllers=1
 +
|channels=4
 +
|width=32 bit
 +
|max bandwidth=47.68 GiB/s
 +
|bandwidth schan=11.92 GiB/s
 +
|bandwidth dchan=23.84 GiB/s
 +
|bandwidth qchan=47.68 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
* PCI Express2.0 (1 lane) x 2 ch
 +
* USB 3.0 Host interface (DRD) × 1 ports (wPHY)
 +
* USB 2.0 Host/Function/OTG interface × 2 ports (wPHY)
 +
* SD Host interface × 4 ch (SDR104)
 +
* Multimedia card interface × 2 ch
 +
* Serial ATA interface × 1 ch
 +
* Media local bus (MLB) Interface × 1 ch (3 pin interface)
 +
* Controller Area Network (CAN-FD support) Interface × 2ch
 +
* Ethernet AVB 1.0-compatible MAC built in Interface: RGMII / Ethernet AVB (802.1BA)
 +
* SYS-DMAC x 48 ch, Realtime-DMAC x 16 ch,
 +
* Audio-DMAC x 32 ch, Audio(peripheral)-DMAC x 29 ch
 +
* 32bit timer x 26 ch
 +
* PWM timer × 7 ch
 +
* I2C bus interface × 7 ch
 +
* Serial communication interface (SCIF) × 11 ch
 +
* Quad serial peripheral interface (QSPI) x 2 ch (for boot, HyperFlash support)
 +
* Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
 +
* Ethernet controller (IEEE802.3u, RMII, without PHY)
 +
* Digital radio interface (DRIF) × 4 ch
 +
 +
== Graphics ==
 +
{{integrated graphics
 +
| gpu                = PowerVR GX6650
 +
| designer            = Imagination Technologies
 +
}}
 +
 +
== Features ==
 +
{{arm features}}

Revision as of 04:47, 23 July 2017

Template:mpu R-Car H3 is a 64-bit nona-core ARM SoC designed by Renesas for the automotive industry and introduced in 2016. The H3 incorporates four Cortex-A57 cores, four Cortex-A53 cores, and a single Cortex-R7 core for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory. This chip incorporates the Imagination's PowerVR GX6650 GPU.

Cache

Main articles: Cortex-A53 § Cache and Cortex-A57 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$640 KiB
655,360 B
0.625 MiB
L1I$352 KiB
360,448 B
0.344 MiB
4x48+5x32 KiB  
L1D$288 KiB
294,912 B
0.281 MiB
9x32 KiB  
L2$2.5 MiB
2,560 KiB
2,621,440 B
0.00244 GiB
     

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4-3200
Supports ECCNo
Controllers1
Channels4
Width32 bit
Max Bandwidth47.68 GiB/s
48,824.32 MiB/s
51.196 GB/s
51,196.01 MB/s
0.0466 TiB/s
0.0512 TB/s
Bandwidth
Single 11.92 GiB/s
Double 23.84 GiB/s
Quad 47.68 GiB/s

Expansions

  • PCI Express2.0 (1 lane) x 2 ch
  • USB 3.0 Host interface (DRD) × 1 ports (wPHY)
  • USB 2.0 Host/Function/OTG interface × 2 ports (wPHY)
  • SD Host interface × 4 ch (SDR104)
  • Multimedia card interface × 2 ch
  • Serial ATA interface × 1 ch
  • Media local bus (MLB) Interface × 1 ch (3 pin interface)
  • Controller Area Network (CAN-FD support) Interface × 2ch
  • Ethernet AVB 1.0-compatible MAC built in Interface: RGMII / Ethernet AVB (802.1BA)
  • SYS-DMAC x 48 ch, Realtime-DMAC x 16 ch,
  • Audio-DMAC x 32 ch, Audio(peripheral)-DMAC x 29 ch
  • 32bit timer x 26 ch
  • PWM timer × 7 ch
  • I2C bus interface × 7 ch
  • Serial communication interface (SCIF) × 11 ch
  • Quad serial peripheral interface (QSPI) x 2 ch (for boot, HyperFlash support)
  • Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
  • Ethernet controller (IEEE802.3u, RMII, without PHY)
  • Digital radio interface (DRIF) × 4 ch

Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR GX6650
DesignerImagination Technologies

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
Retrieved from "https://en.wikichip.org/w/index.php?title=renesas/r-car/h3&oldid=56118"
Facts about "R-Car H3 - Renesas"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
R-Car H3 - Renesas#package +
core count9 +
core nameCortex-A53 +, Cortex-A57 + and Cortex-R7 +
core voltage0.8 V (8 dV, 80 cV, 800 mV) +
designerRenesas + and ARM Holdings +
die area111.36 mm² (0.173 in², 1.114 cm², 111,360,000 µm²) +
die length12.94 mm (1.294 cm, 0.509 in, 12,940 µm) +
die width8.61 mm (0.861 cm, 0.339 in, 8,610 µm) +
familyR-Car +
first announcedDecember 2, 2015 +
first launchedMarch 2018 +
full page namerenesas/r-car/h3 +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuPowerVR GX6650 +
integrated gpu designerImagination Technologies +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) +
isaARMv8 +
isa familyARM +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + and 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
ldateMarch 2018 +
main imageFile:r-car h3.png +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory bandwidth47.68 GiB/s (48,824.32 MiB/s, 51.196 GB/s, 51,196.01 MB/s, 0.0466 TiB/s, 0.0512 TB/s) +
max memory channels4 +
microarchitectureCortex-A53 +, Cortex-A57 + and Cortex-R7 +
model numberH3 +
nameR-Car H3 +
packageFCBGA-1384 +
part numberR8A77950 +
process16 nm (0.016 μm, 1.6e-5 mm) +
series3rd Gen +
smp max ways1 +
supported memory typeLPDDR4-3200 +
technologyCMOS +
thread count9 +
word size64 bit (8 octets, 16 nibbles) +