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Difference between revisions of "renesas/r-car/m3 (sip)"
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{{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a57#Memory_Hierarchy|l1=Cortex-A53 § Cache|l2=Cortex-A57 § Cache}} | {{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a57#Memory_Hierarchy|l1=Cortex-A53 § Cache|l2=Cortex-A57 § Cache}} | ||
{{cache size | {{cache size | ||
| − | |l1 cache= | + | |l1 cache=480 KiB |
|l1i cache=256 KiB | |l1i cache=256 KiB | ||
|l1i break=2x48+5x32 KiB | |l1i break=2x48+5x32 KiB | ||
| − | |l1d cache= | + | |l1d cache=224 KiB |
| − | |l1d break= | + | |l1d break=7x32 KiB |
|l2 cache=1.5 MiB | |l2 cache=1.5 MiB | ||
}} | }} | ||
Revision as of 03:46, 23 July 2017
Template:mpu R-Car M3 is a 64-bit hepta-core ARM SoC designed by Renesas for the automotive industry and introduced in 2016. The M3 incorporates four Cortex-A53 cores, two Cortex-A57, and an additional Cortex-R7 core for real-time processing. This chip supports up to dual-channel LPDDR4-3200 memory.
This model is an SiP variant of the M3 which include the DDR memory on-package.
Cache
- Main articles: Cortex-A53 § Cache and Cortex-A57 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Facts about "R-Car M3 (SiP) - Renesas"
| has ecc memory support | false + |
| l1$ size | 480 KiB (491,520 B, 0.469 MiB) + |
| l1d$ size | 224 KiB (229,376 B, 0.219 MiB) + |
| l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l2$ size | 1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) + |
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
| max memory channels | 2 + |
| supported memory type | LPDDR4-3200 + |