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− | '''Helio P10 M''' ('''MT6755M''') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and introduced in early-[[2016]]. This SoC, which incorporates eight {{armh|Cortex-A53|l=arch}} cores and is manufactured on [[TSMC]]'s [[28 nm process]], operates at up to 1.8 GHz and supports single-channel LPDDR3- | + | '''Helio P10 M''' ('''MT6755M''') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and introduced in early-[[2016]]. This SoC, which incorporates eight {{armh|Cortex-A53|l=arch}} cores and is manufactured on [[TSMC]]'s [[28 nm process]], operates at up to 1.8 GHz and supports up to 4 GiB of single-channel LPDDR3-1866 memory. This chip incorporates the {{imgtec|Mali-T880}} [[IGP]] operating at 650 MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) category 6. |
This processor is made of two independent clusters of {{armh|Cortex-A53|l=arch}} with four cores each linked together via a {{armh|CCI-400}}. The two clusters have a maximum operating frequency of 1.8 GHz and 1.2 GHz respectively. | This processor is made of two independent clusters of {{armh|Cortex-A53|l=arch}} with four cores each linked together via a {{armh|CCI-400}}. The two clusters have a maximum operating frequency of 1.8 GHz and 1.2 GHz respectively. |
Revision as of 17:14, 12 July 2017
Template:mpu Helio P10 M (MT6755M) is a 64-bit octa-core ARM LTE system on a chip designed by MediaTek and introduced in early-2016. This SoC, which incorporates eight Cortex-A53 cores and is manufactured on TSMC's 28 nm process, operates at up to 1.8 GHz and supports up to 4 GiB of single-channel LPDDR3-1866 memory. This chip incorporates the Mali-T880 IGP operating at 650 MHz. This SoC has a modem supporting LTE User Equipment (UE) category 6.
This processor is made of two independent clusters of Cortex-A53 with four cores each linked together via a CCI-400. The two clusters have a maximum operating frequency of 1.8 GHz and 1.2 GHz respectively.
The 'M' verison (MT6755M) is identical to the regular MT6755 except for the GPU and CPU lower clock speeds.
Contents
Cache
- Main article: Cortex-A53 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Graphics
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Integrated Graphics Information
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Wireless
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4G |
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Image
- Integrated image signal processor supports 21 MP
- Supports image stabilization
- Supports video stabilization
- Supports noise reduction
- Supports lens shading correction
- Supports AE/AWB/AF
- Supports edge enhancement
- Supports face detection and visual tracking
- Hardware JPEG encoder
Video
- HEVC decoder 4k2k @ 30fps
- H.264 decoder (30fps/40Mbps)
- Sorenson H.263/H.263 decoder (1080p @ 60fps/40Mbps)
- MPEG-4 SP/ASP decoder (1080p @ 60fps/40Mbps)
- DIVX4/DIVX5/DIVX6/DIVX HD/XVID decoder (1080p @ 60fps/40Mbps)
- VP8 / VC-1 decoders
- MPEG-4 / H.263 / H.264 / HEVC encoders
Audio
- Audio content sampling rates 8kHz to 192kHz
- Audio content sampling format 8-bit/16-bit/24-bit Mono/Stereo
- I2S, PCM
- Encode: AMR-NB, AMR-WB, AAC, OGG, ADPCM
- Decode: WAV, MP3, MP2, AAC, AMR-NB, AMR-WB, MIDI, Vorbis, APE, AAC-plus v1, AAC-plus v2, FLAC, WMA, ADPCM
- 7.1 channel MHL output
Utilizing devices
- Alcatel Pop 4S
- Alcatel Flash Plus 2
- Gionee M6
- Gionee S6 Pro
- InFocus S1
- TP-Link Neffos X1
- Vernee Mars
- Meizu M3 Note
This list is incomplete; you can help by expanding it.