From WikiChip
Difference between revisions of "intel/xeon e3/e3-1240 v5"
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== Memory controller == | == Memory controller == | ||
{{memory controller | {{memory controller | ||
− | |type=DDR3L-1600 | + | |type=DDR3L-1600 |
|type 2=DDR4-2133 | |type 2=DDR4-2133 | ||
|ecc=Yes | |ecc=Yes | ||
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|controllers=1 | |controllers=1 | ||
|channels=2 | |channels=2 | ||
− | |max bandwidth= | + | |max bandwidth=31.79 GiB/s |
− | |bandwidth schan= | + | |bandwidth schan=15.89 GiB/s |
− | |bandwidth dchan= | + | |bandwidth dchan=31.79 GiB/s |
}} | }} | ||
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This chip has no integrated graphics processing unit. | This chip has no integrated graphics processing unit. | ||
− | == Features == | + | == Features == |
{{x86 features | {{x86 features | ||
|real=Yes | |real=Yes | ||
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|bpt=No | |bpt=No | ||
|eist=Yes | |eist=Yes | ||
− | |sst= | + | |sst=No |
|flex=No | |flex=No | ||
|fastmem=No | |fastmem=No | ||
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|att=No | |att=No | ||
|ipt=No | |ipt=No | ||
− | |tsx= | + | |tsx=No |
− | |txt= | + | |txt=No |
− | |ht= | + | |ht=No |
− | |vpro= | + | |vpro=No |
|vtx=Yes | |vtx=Yes | ||
|vtd=Yes | |vtd=Yes | ||
|ept=Yes | |ept=Yes | ||
− | |mpx= | + | |mpx=No |
|sgx=Yes | |sgx=Yes | ||
|securekey=Yes | |securekey=Yes | ||
− | |osguard= | + | |osguard=No |
|3dnow=No | |3dnow=No | ||
|e3dnow=No | |e3dnow=No | ||
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|amdvi=No | |amdvi=No | ||
|amdv=No | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
|rvi=No | |rvi=No | ||
|smt=No | |smt=No |
Revision as of 16:22, 8 July 2017
Template:mpu Xeon E3-1240 v5 is an entry-level server and workstation 64-bit quad-core x86 microprocessor introduced by Intel in October 2015. This Skylake-based chip operates at 3.5 GHz with turbo boost of 3.9 GHz. The E3-1240 V5 has a TDP of 80 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has no integrated graphics processor.
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Graphics
This chip has no integrated graphics processing unit.
Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Xeon E3-1240 v5 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E3-1240 v5 - Intel#io + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Software Guard Extensions + and Secure Key Technology + |
has intel enhanced speedstep technology | true + |
has intel secure key technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 16 + |
supported memory type | DDR3L-1600 + and DDR4-2133 + |
x86/has software guard extensions | true + |