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Difference between revisions of "intel/core i3/i3-6100e"
< intel‎ | core i3

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|bandwidth schan=15.89 GiB/s
 
|bandwidth schan=15.89 GiB/s
 
|bandwidth dchan=31.79 GiB/s
 
|bandwidth dchan=31.79 GiB/s
 +
}}
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== Expansions ==
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{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 16
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| pcie config        = 1x16
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| pcie config 2      = 2x8
 +
| pcie config 3      = 1x8+2x4
 
}}
 
}}
  
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}}
 
}}
 
{{skylake hardware accelerated video table|col=1}}
 
{{skylake hardware accelerated video table|col=1}}
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== Expansions ==
 
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{{mpu expansions
 
−
| pcie revision      = 3.0
 
−
| pcie lanes        = 16
 
−
| pcie config        = 1x16
 
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| pcie config 1      = 2x8
 
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| pcie config 2      = 1x8+2x4
 
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| usb revision      =
 
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| usb revision 2    =
 
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| usb ports          =
 
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| sata ports        =
 
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| integrated lan    =
 
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| uart              =
 
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| gp io              =
 
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}}
 
  
 
== Features ==  
 
== Features ==  

Revision as of 01:40, 8 July 2017

Template:mpu Core i3-6100E is a 64-bit dual-core x86 low-end performance mobile microprocessor introduced by Intel late 2015. This processor, which is based on the Skylake microarchitecture and manufactured on a 14 nm process, has a base frequency of 2.7 GHz with a TDP of 35 W. This processor incorporates the HD Graphics 530 GPU clocked at 350 MHz with a max frequency of 950 MHz.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB4-way set associativewrite-back
L3$3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
  2x1.5 MiB write-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR3-1866, DDR3L-1600, DDR4-2133
Supports ECCYes
Max Mem64 GiB
Controllers1
Channels2
Max Bandwidth31.79 GiB/s
32,552.96 MiB/s
34.134 GB/s
34,134.253 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes16
Configs1x16, 2x8, 1x8+2x4


Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUHD Graphics 530
DesignerIntelDevice ID0x191B
Execution Units24Max Displays3
Max Memory64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
Frequency350 MHz
0.35 GHz
350,000 KHz
Burst Frequency950 MHz
0.95 GHz
950,000 KHz
OutputDP, eDP, HDMI, DVI
Max Resolution
HDMI4096x2304 @24 Hz
DP4096x2304 @60 Hz
eDP4096x2304 @60 Hz
Standards
DirectX12
OpenGL4.4
OpenCL2.0
DP1.2
eDP1.3
HDMI1.4a
Additional Features
Intel Quick Sync Video
Intel InTru 3D
Intel Clear Video
Intel Clear Video HD

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i3/i3-6100e&oldid=53041"
Facts about "Core i3-6100E - Intel"
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"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Core i3-6100E - Intel#io +
device id0x191B +
has ecc memory supporttrue +
integrated gpuHD Graphics 530 +
integrated gpu base frequency350 MHz (0.35 GHz, 350,000 KHz) +
integrated gpu designerIntel +
integrated gpu execution units24 +
integrated gpu max frequency950 MHz (0.95 GHz, 950,000 KHz) +
integrated gpu max memory65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB) +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ size3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
max memory bandwidth31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels2 +
max pcie lanes16 +
supported memory typeLPDDR3-1866 +, DDR3L-1600 + and DDR4-2133 +