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Difference between revisions of "intel/xeon e3/e3-1578l v5"
| Line 67: | Line 67: | ||
|l3 break=4x2 MiB | |l3 break=4x2 MiB | ||
|l3 policy=write-back | |l3 policy=write-back | ||
| + | }} | ||
| + | |||
| + | == Memory controller == | ||
| + | {{memory controller | ||
| + | |type=LPDDR3-1866 | ||
| + | |type 2=DDR3L-1600 | ||
| + | |type 3=DDR4-2133 | ||
| + | |ecc=Yes | ||
| + | |max mem=64 GiB | ||
| + | |controllers=1 | ||
| + | |channels=2 | ||
| + | |max bandwidth=31.79 GiB/s | ||
| + | |bandwidth schan=15.89 GiB/s | ||
| + | |bandwidth dchan=31.79 GiB/s | ||
}} | }} | ||
Revision as of 00:17, 8 July 2017
Template:mpu Xeon E3-1578L v5 is a 64-bit quad-core x86 mobile workstation microprocessor introduced by Intel in early-2016. This processor, which is based on the Skylake microarchitecture, is manufactured on Intel's 14 nm process. The E3-1578L v5 operates at 2.0 GHz with a TDP of 45 W and with a Turbo Boost frequency of 3.4 GHz for a single active core. This MPU supports up to 64 GiB of dual-channel ECC DDR4-2133 memory and incorporates Intel's Iris Pro Graphics P580 IGP operating at 700 MHz with a burst frequency of 1 GHz.
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Facts about "Xeon E3-1578L v5 - Intel"
| has ecc memory support | true + |
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
| max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
| max memory channels | 2 + |
| supported memory type | LPDDR3-1866 +, DDR3L-1600 + and DDR4-2133 + |