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Difference between revisions of "intel/xeon e3/e3-1585 v5"
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|model number=E3-1585 v5 | |model number=E3-1585 v5 | ||
|s-spec=SR2RB | |s-spec=SR2RB | ||
+ | |market=Server | ||
+ | |first announced=May 31, 2016 | ||
+ | |first launched=May 31, 2016 | ||
+ | |release price=$556.00 | ||
|family=Xeon E3 | |family=Xeon E3 | ||
|series=E3-1500 v5 | |series=E3-1500 v5 | ||
Line 25: | Line 29: | ||
|thread count=8 | |thread count=8 | ||
|max cpus=1 | |max cpus=1 | ||
+ | |max memory=64 GiB | ||
+ | |v core min=0.55 V | ||
+ | |v core max=1.52 V | ||
|tdp=65 W | |tdp=65 W | ||
+ | |tjunc min=0 °C | ||
+ | |tjunc max=100 °C | ||
+ | |tstorage min=-25 °C | ||
+ | |tstorage max=125 °C | ||
|package module 1={{packages/intel/fcbga-1440}} | |package module 1={{packages/intel/fcbga-1440}} | ||
}} | }} |
Revision as of 00:23, 8 July 2017
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Xeon E3-1585 v5 - Intel"
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |