From WikiChip
Difference between revisions of "intel/core i5/i5-6350hq"
Line 7: | Line 7: | ||
|model number=i5-6350HQ | |model number=i5-6350HQ | ||
|s-spec=SR2QZ | |s-spec=SR2QZ | ||
+ | |market=Mobile | ||
+ | |first announced=January 2, 2016 | ||
+ | |first launched=January 2, 2016 | ||
+ | |release price=$306.00 | ||
|family=Core i5 | |family=Core i5 | ||
|series=i5-6000 | |series=i5-6000 | ||
Line 23: | Line 27: | ||
|word size=64 bit | |word size=64 bit | ||
|core count=4 | |core count=4 | ||
− | |thread count= | + | |thread count=4 |
|max cpus=1 | |max cpus=1 | ||
+ | |max memory=64 GiB | ||
+ | |v core min=0.55 V | ||
+ | |v core max=1.52 V | ||
|tdp=45 W | |tdp=45 W | ||
+ | |ctdp down=35 W | ||
+ | |tjunc min=0 °C | ||
+ | |tjunc max=100 °C | ||
+ | |tstorage min=-25 °C | ||
+ | |tstorage max=125 °C | ||
|package module 1={{packages/intel/fcbga-1440}} | |package module 1={{packages/intel/fcbga-1440}} | ||
}} | }} |
Revision as of 23:23, 7 July 2017
Cache
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Core i5-6350HQ - Intel"
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + |