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Difference between revisions of "intel/core i3/6120t"
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{{intel title|Core i3-6120T}}
 
{{intel title|Core i3-6120T}}
 
{{mpu
 
{{mpu
−
| name               = Intel Core i3-6120T
+
|name=Intel Core i3-6120T
−
| no image           = Yes
+
|no image=Yes
−
| image              =
+
|designer=Intel
−
| image size          =
+
|manufacturer=Intel
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| caption            =
+
|model number=i3-6120T
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| designer           = Intel
+
|part number=CM8066201927104
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| manufacturer       = Intel
+
|s-spec=SR2HF
−
| model number       = i3-6120T
+
|market=Desktop
−
| part number         = CM8066201927104
+
|first announced=May 9, 2016
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| part number 2      =
+
|first launched=June 3, 2016
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| part number 3      =
+
|family=Core i3
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| part number 4      =
+
|series=6100
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| part number 5      =  
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|locked=Yes
−
| market             = Desktop
+
|bus type=DMI 3.0
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| first announced     = May 9, 2016
+
|bus rate=8 GT/s
−
| first launched     = June 3, 2016
+
|isa=x86-64
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| last order          =
+
|isa family=x86
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| last shipment      =
+
|microarch=Skylake
−
 
+
|core family=6
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| family             = Core i3
+
|process=14 nm
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| series             = 6100
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|word size=64 bits
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| locked             = Yes
+
|core count=2
−
| frequency          =
+
|thread count=4
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| turbo frequency    =
+
|max cpus=1
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| turbo frequency1  =
+
|max memory=64 GiB
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| turbo frequency2  =
 
−
| turbo frequency3  =
 
−
| turbo frequency4  =
 
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| bus type           = DMI 3.0
 
−
| bus speed          =
 
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| bus rate           = 8 GT/s
 
−
| clock multiplier  =  
 
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| s-spec            = SR2HF
 
−
 
 
−
| isa family         = x86
 
−
| isa                = x86-64
 
−
| microarch         = Skylake  
 
−
| platform          =
 
−
| core name          =
 
−
| core stepping      =  
 
−
| process           = 14 nm
 
−
| die size          =
 
−
| word size         = 64 bits
 
−
| core count         = 2
 
−
| thread count       = 4
 
−
| max cpus           = 1
 
−
| max memory         = 64 GiB
 
−
 
 
−
| electrical          =
 
−
| sdp                =
 
−
| tdp                =
 
−
| ctdp down          =
 
−
| ctdp down frequency =
 
−
| ctdp up            =
 
−
| ctdp up frequency  =
 
−
| temp max            =
 
−
| temp min            =
 
−
 
 
−
| packaging          =
 
−
| package            =
 
−
| package type        =
 
−
| package pitch      =
 
−
| package size        =
 
−
| socket              =
 
 
}}
 
}}
 
'''Core i3-6120T''' is a {{arch|64}} [[dual-core]] low-end performance [[microprocessor]] set to be introduced by [[Intel]] in 2016.
 
'''Core i3-6120T''' is a {{arch|64}} [[dual-core]] low-end performance [[microprocessor]] set to be introduced by [[Intel]] in 2016.

Revision as of 14:04, 6 July 2017

Template:mpu Core i3-6120T is a 64-bit dual-core low-end performance microprocessor set to be introduced by Intel in 2016.



DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Skylake § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB 8-way set associative (per core, write-back)
L1D$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB 8-way set associative (per core, write-back)
L2$ 512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
2x256 KiB 4-way set associative (per core, write-back)
L3$ 3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
shared

Expansions

Template:mpu expansions

Features

Template:mpu features

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Facts about "Core i3-6120T - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ descriptionshared +
l3$ size3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +