From WikiChip
Difference between revisions of "cavium/octeon plus/cn5850-1000bg1521-scp"
m (Bot: change package to new layout) |
m (Bot: corrected param) |
||
Line 10: | Line 10: | ||
| model number = CN5850-1000 SCP | | model number = CN5850-1000 SCP | ||
| part number = CN5850-1000BG1521-SCP | | part number = CN5850-1000BG1521-SCP | ||
− | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
+ | | part number 4 = | ||
| market = Network | | market = Network | ||
| first announced = October 9, 2006 | | first announced = October 9, 2006 |
Revision as of 18:13, 30 June 2017
Template:mpu CN5850-1000 SCP is a 64-bit dodeca-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2007. This processor, which incorporates twelve cnMIPS cores, operates at 1 GHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of secure communication software such as encryption, compression/decompression, and TCP acceleration.
Contents
Cache
- Main article: cnMIPS § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||
|
Memory controller
![]() |
Integrated Memory Controller
|
|||||||||||||
|
Expansions
![]() |
Expansion Options
|
|||||||||||||||
|
Networking
![]() |
Networking
|
|||||||
|
Hardware Accelerators
[Edit/Modify Accelerators Info]
![]() |
Hardware Accelerators
|
|||||||||||
|
Block diagram
Datasheet
Facts about "CN5850-1000 SCP - Cavium"
has ecc memory support | true + |
has hardware accelerators for cryptography | true + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for tcp packet processing | true + |
l1$ size | 576 KiB (589,824 B, 0.563 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l1i$ description | 64-way set associative + |
l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
max memory channels | 1 + |
supported memory type | DDR2-800 + |