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Difference between revisions of "cavium/octeon/cn3630-500bg1521-exp"
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| model number = CN3630-500 EXP | | model number = CN3630-500 EXP | ||
| part number = CN3630-500BG1521-EXP | | part number = CN3630-500BG1521-EXP | ||
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| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
+ | | part number 4 = | ||
| market = Networking | | market = Networking | ||
| first announced = August, 2005 | | first announced = August, 2005 |
Revision as of 17:56, 30 June 2017
Template:mpu The CN3630-500 EXP is a 64-bit quad-core MIPS communication microprocessor designed by Cavium and introduced in 2005. This processor, which incorporates four cnMIPS cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
Contents
Cache
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Networking
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Networking
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Hardware Accelerators
[Edit/Modify Accelerators Info]
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Hardware Accelerators
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Block diagram
Datasheet
Facts about "CN3630-500 EXP - Cavium"