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Difference between revisions of "intel/celeron/3865u"
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{{intel title|Celeron 3865U}}
 
{{intel title|Celeron 3865U}}
 
{{mpu
 
{{mpu
| name               = Celeron 3865U
+
|name=Celeron 3865U
| no image           = Yes
+
|no image=Yes
| image              =
+
|designer=Intel
| image size          =
+
|manufacturer=Intel
| caption            =
+
|model number=3865U
| designer           = Intel
+
|market=Mobile
| manufacturer       = Intel
+
|first announced=January 3, 2017
| model number       = 3865U
+
|first launched=January 3, 2017
| part number        =
+
|family=Celeron
| part number 1      =
+
|series=3800
| s-spec              =
+
|locked=Yes
| market             = Mobile
+
|frequency=1,800 MHz
| first announced     = January 3, 2017
+
|bus type=OPI
| first launched     = January 3, 2017
+
|bus rate=4 GT/s
| last order          =
+
|clock multiplier=22
| last shipment      =
+
|cpuid=306A9
| release price      =
+
|isa=x86-64
 
+
|isa family=x86
| family             = Celeron
+
|microarch=Kaby Lake
| series             = 3800
+
|platform=Kaby Lake
| locked             = Yes
+
|core name=Kaby Lake U
| frequency           = 1,800 MHz
+
|core family=6
| bus type           = OPI
+
|core model=142
| bus speed          =
+
|process=14 nm
| bus rate           = 4 GT/s
+
|technology=CMOS
| bus links          =
+
|word size=64 bit
| clock multiplier   = 22
+
|core count=2
| cpuid               = 306A9
+
|thread count=2
 
+
|max cpus=1
| isa family          = x86
+
|max memory=64 GiB
| isa                 = x86-64
+
|v core min=0.25 V
| microarch           = Kaby Lake
+
|v core max=1.52 V
| platform           = Kaby Lake
+
|tdp=15 W
| chipset            =
+
|ctdp down=10 W
| chipset 2          =
+
|tjunc min=0 °C
| core name           = Kaby Lake U
+
|tjunc max=100 °C
| core family         = 6
+
|tstorage min=-25 °C
| core model         = 58
+
|tstorage max=125 °C
| core stepping      =
 
| core stepping 2    =  
 
| process             = 14 nm
 
| transistors        =
 
| technology         = CMOS
 
| die area            =
 
| die width          =
 
| die length          =
 
| word size           = 64 bit
 
| core count         = 2
 
| thread count       = 2
 
| max cpus           = 1
 
| max memory         = 64 GiB
 
 
 
 
 
| v core min         = 0.25 V
 
| v core max         = 1.52 V
 
| tdp                 = 15 W
 
| tdp typical        =
 
| ctdp down           = 10 W
 
| ctdp down frequency =
 
| ctdp up            =
 
| ctdp up frequency  =
 
| tjunc min           = 0 °C
 
| tjunc max           = 100 °C
 
| tcase min          =
 
| tcase max          =
 
| tstorage min       = -25 °C
 
| tstorage max       = 125 °C
 
| tambient min        =
 
| tambient max        =
 
 
 
 
|package module 1={{packages/intel/fcbga-1356}}
 
|package module 1={{packages/intel/fcbga-1356}}
 
}}
 
}}

Revision as of 04:39, 27 June 2017

Template:mpu Celeron 3865U is a 64-bit dual-core budget x86 mobile microprocessors introduced by Intel in early 2017. The 3865U, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's improved 14nm+ process. This processor operates at 1.8 GHz with a TDP of 15 W and supports up to 32 GiB of dual-channel non-ECC DDR4-2133. Additionally the 3865U incorporates Intel's HD Graphics 610 IGP operating at 300 MHz with a burst frequency of 900 GHz.

This model has a configurable TDP-down of 10 W.

Cache

Main article: Kaby Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back

L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB4-way set associativewrite-back

L3$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  2x1 MiB12-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR3-1866, DDR3L-1600, DDR4-2133
Supports ECCNo
Max Mem64 GiB
Controllers1
Channels2
Max Bandwidth31.79 GiB/s
32,552.96 MiB/s
34.134 GB/s
34,134.253 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes16
Configs1x16, 2x8, 1x8+2x4


Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUHD Graphics 610
DesignerIntelDevice ID0x5906
Execution Units12Max Displays3
Max Memory32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
Frequency300 MHz
0.3 GHz
300,000 KHz
Burst Frequency900 MHz
0.9 GHz
900,000 KHz
OutputDP, eDP, HDMI, DVI

Max Resolution
HDMI4096x2304 @24 Hz
DP4096x2304 @60 Hz
eDP4096x2304 @60 Hz

Standards
DirectX12
OpenGL4.4
OpenCL2.0
DP1.2
eDP1.4
HDMI1.4a

Additional Features
Intel Quick Sync Video
Intel Clear Video
Intel Clear Video HD

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
MPXMemory Protection Extensions
SGXSoftware Guard Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
Flex MemoryFlex Memory Access
ISRTSmart Response Technology
MWTMy WiFi Technology
Facts about "Celeron 3865U - Intel"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Celeron 3865U - Intel#io +
device id0x5906 +
has ecc memory supportfalse +
has extended page tables supporttrue +
has featureAdvanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology + and My WiFi Technology +
has intel enhanced speedstep technologytrue +
has intel flex memory access supporttrue +
has intel my wifi technology supporttrue +
has intel secure key technologytrue +
has intel smart response technology supporttrue +
has intel speed shift technologytrue +
has intel supervisor mode execution protectiontrue +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has x86 advanced encryption standard instruction set extensiontrue +
integrated gpuHD Graphics 610 +
integrated gpu base frequency300 MHz (0.3 GHz, 300,000 KHz) +
integrated gpu designerIntel +
integrated gpu execution units12 +
integrated gpu max frequency900 MHz (0.9 GHz, 900,000 KHz) +
integrated gpu max memory32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB) +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ description12-way set associative +
l3$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
max memory bandwidth31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels2 +
max pcie lanes16 +
supported memory typeLPDDR3-1866 +, DDR3L-1600 + and DDR4-2133 +
x86/has memory protection extensionstrue +
x86/has software guard extensionstrue +