-
WikiChip
WikiChip
-
Architectures
Popular x86
-
Intel
- Client
- Server
- Big Cores
- Small Cores
-
AMD
Popular ARM
-
ARM
- Server
- Big
- Little
-
Cavium
-
Samsung
-
-
Chips
Popular Families
-
Ampere
-
Apple
-
Cavium
-
HiSilicon
-
MediaTek
-
NXP
-
Qualcomm
-
Renesas
-
Samsung
-
From WikiChip
Difference between revisions of "amd/am8086/d8086b"
(→Cache) |
m (Bot: corrected mem) |
||
Line 44: | Line 44: | ||
| thread count = | | thread count = | ||
| max cpus = 1 | | max cpus = 1 | ||
− | | max memory = 1 | + | | max memory = 1 MiB |
| max memory addr = 0xFFFFF | | max memory addr = 0xFFFFF | ||
Revision as of 02:54, 23 June 2017
Template:mpu D8086B is a second-sourced 8086 designed by Intel and manufactured by AMD in a 40-pin Ceramic DIP. This chip operated at 5 MHz.
Contents
Cache
- Main article: 8086 § Cache
Cache Info [Edit Values] | ||
L1$ | 0 KiB 0 B 0 MiB |
1x0 KiB |
Features
- Burn-in screening
- ISA-compatible with 8080
- Direct addressing up to 1 MB
- 16-bit arithmetic
Documents
Datasheets
- Am8086 (01966, Rev B); Publication #01966 Rev B.
- Am8086 (01966, Rev D); Publication #01966 Rev D.