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Difference between revisions of "amd/k6-2/k6-2-300afr"
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| thread count        = 1
 
| thread count        = 1
 
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| max cpus            = 1
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| max memory          = 4 GB
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| max memory          = 4 GiB
  
 
| electrical          = Yes
 
| electrical          = Yes

Revision as of 01:44, 23 June 2017

Template:mpu K6-2/300AFR was a 32-bit x86 K6-2-based microprocessor designed and manufactured in 1998 by AMD. Manufactured using a 0.25 µm process, this MPU operated at 300 MHz with a FSB of 100 MHz consumed 17.2 W. Note that K6-2/300AFR-66 is an identical model with a multiplier of 4.5 instead of 3 designed to support a 66 MHz bus instead.

Cache

Main article: K6-2 § Cache

L2$ can be 512 KiB to 2 MiB, depending on manufacturer and motherboard model. L2$ is off-chip.

Cache Info [Edit Values]
L1I$ 32 KiB
32,768 B
0.0313 MiB
1x32 KiB 2-way set associative
L1D$ 32 KiB
32,768 B
0.0313 MiB
1x32 KiB 2-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Features

Template:mpu features

  • Auto-power down state
  • Stop clock state

Gallery

  • Week 35, 1998

  • Week 42, 1998

  • Week 51, 1998

  • AMD-K6-2 300AFR.jpg

Documents

DataSheet

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/k6-2/k6-2-300afr&oldid=46576"
Facts about "K6-2/300AFR - AMD"
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l1d$ description2-way set associative +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description2-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +