Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/80486/486dx2-50"
(→Cache) |
m (Bot: corrected mem) |
||
| Line 64: | Line 64: | ||
| core count = 1 | | core count = 1 | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 4 | + | | max memory = 4 GiB |
| electrical = Yes | | electrical = Yes | ||
Revision as of 01:41, 23 June 2017
Template:mpu i486DX2-50 was a fourth-generation x86 microprocessor introduced by Intel in 1992. This chip, which is based on the 80486 microarchitecture, had a clock doubler operating at 50 MHz, twice the bus frequency. Like the original i486DX, this chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM).
Contents
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KiB 8,192 B 0.00781 MiB |
1x8 KiB 4-way set associative (unified, write-through policy) |
Graphics
This chip had no integrated graphics processing unit.
Features
- System Management Mode (SMM)
Gallery
A80486DX2-50, S-Spec SX808
A80486DX2-50, S-Spec SX641
SB80486DX2-50, S-Spec SX920
SB80486DX2-50, S-Spec SX825
.png)
See also
Facts about "i486DX2-50 - Intel"
| l1$ description | 4-way set associative + |
| l1$ size | 8 KiB (8,192 B, 0.00781 MiB) + |