Semiconductor & Computer Engineering
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Difference between revisions of "intel/xeon gold/6148"
| Line 25: | Line 25: | ||
| series = 6100 | | series = 6100 | ||
| locked = Yes | | locked = Yes | ||
| − | | frequency = 2 | + | | frequency = 2,400 MHz |
| − | | turbo frequency = | + | | turbo frequency = Yes |
| − | | turbo frequency1 = | + | | turbo frequency1 = 3,700 MHz |
| turbo frequency2 = | | turbo frequency2 = | ||
| turbo frequency3 = | | turbo frequency3 = | ||
| Line 77: | Line 77: | ||
| v io 3 = | | v io 3 = | ||
| sdp = | | sdp = | ||
| − | | tdp = | + | | tdp = 150 W |
| tdp typical = | | tdp typical = | ||
| ctdp down = | | ctdp down = | ||
| Line 108: | Line 108: | ||
| socket 0 type = LGA | | socket 0 type = LGA | ||
}} | }} | ||
| − | '''Xeon Gold 6148''' is a {{arch|64}} [[x86]] high-performance server [[icosa-core]] [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6148 operates at 2.4 GHz. | + | '''Xeon Gold 6148''' is a {{arch|64}} [[x86]] high-performance server [[icosa-core]] [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6148 operates at 2.4 GHz with a TDP of 150 W and a {{intel|Turbo Boost|turbo frequency}} of 3.7 GHz. |
Revision as of 11:33, 4 June 2017
Template:mpu Xeon Gold 6148 is a 64-bit x86 high-performance server icosa-core multiprocessor set to be introduced by Intel in the second quarter of 2017. This processor is based on the server configuration of the Skylake microarchitecture (a Skylake SP core) and is manufactured on Intel's 14 nm process. The 6148 operates at 2.4 GHz with a TDP of 150 W and a turbo frequency of 3.7 GHz.
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Features
[Edit/Modify Supported Features]
Facts about "Xeon Gold 6148 - Intel"
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has ecc memory support | true + |
| has extended page tables support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions + and OS Guard + |
| has intel enhanced speedstep technology | true + |
| has intel supervisor mode execution protection | true + |
| has intel vpro technology | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has transactional synchronization extensions | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| l1$ size | 1,280 KiB (1,310,720 B, 1.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 640 KiB (655,360 B, 0.625 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 640 KiB (655,360 B, 0.625 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) + |
| l3$ description | 11-way set associative + |
| l3$ size | 27.5 MiB (28,160 KiB, 28,835,840 B, 0.0269 GiB) + |
| max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
| max memory channels | 6 + |
| supported memory type | DDR4-2666 + |
| x86/has memory protection extensions | true + |