Semiconductor & Computer Engineering
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Difference between revisions of "intel/core i9/i9-7960x"
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| package module 1 = {{packages/intel/lga-2066}} | | package module 1 = {{packages/intel/lga-2066}} | ||
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| − | '''Core i9-7960X''' is a {{arch|64}} [[hexadeca-core]] high-performance [[x86]] desktop microprocessor introduced by [[Intel]] in mid-[[2017]]. This chip, which is based on the {{intel|Skylake|l=arch}} microarchitecture, is fabricated on Intel's [[14 nm process]]. The i7-7960X operates at ? GHz with a TDP of 160 W and a {{intel|Turbo Boost}} frequency of ? GHz. The processor supports up to 128 GiB of | + | '''Core i9-7960X''' is a {{arch|64}} [[hexadeca-core]] high-performance [[x86]] desktop microprocessor introduced by [[Intel]] in mid-[[2017]]. This chip, which is based on the {{intel|Skylake|l=arch}} microarchitecture, is fabricated on Intel's [[14 nm process]]. The i7-7960X operates at ? GHz with a TDP of 160 W and a {{intel|Turbo Boost}} frequency of ? GHz. The processor supports up to 128 GiB of quad-channel DDR4-2666 memory. |
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|ecc=No | |ecc=No | ||
|max mem= | |max mem= | ||
| − | |channels= | + | |channels=4 |
| − | |max bandwidth= | + | |max bandwidth=79.47 GiB/s |
|bandwidth schan=19.89 GiB/s | |bandwidth schan=19.89 GiB/s | ||
|bandwidth dchan=39.72 GiB/s | |bandwidth dchan=39.72 GiB/s | ||
|bandwidth qchan=79.47 GiB/s | |bandwidth qchan=79.47 GiB/s | ||
| − | |||
}} | }} | ||
Revision as of 22:56, 3 June 2017
Template:mpu Core i9-7960X is a 64-bit hexadeca-core high-performance x86 desktop microprocessor introduced by Intel in mid-2017. This chip, which is based on the Skylake microarchitecture, is fabricated on Intel's 14 nm process. The i7-7960X operates at ? GHz with a TDP of 160 W and a Turbo Boost frequency of ? GHz. The processor supports up to 128 GiB of quad-channel DDR4-2666 memory.
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Graphics
This processor has no integrated graphics.
Features
[Edit/Modify Supported Features]
Facts about "Core i9-7960X - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i9-7960X - Intel#io + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has ecc memory support | false + |
| has extended page tables support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Turbo Boost Technology 2.0 +, Turbo Boost Max Technology 3.0 +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions + and Software Guard Extensions + |
| has intel enhanced speedstep technology | true + |
| has intel turbo boost max technology 3 0 | true + |
| has intel turbo boost technology 2 0 | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has second level address translation support | true + |
| has transactional synchronization extensions | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| l1$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) + |
| max memory bandwidth | 79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) + |
| max memory channels | 4 + |
| max pcie lanes | 44 + |
| supported memory type | DDR4-2666 + |
| x86/has memory protection extensions | true + |
| x86/has software guard extensions | true + |