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Difference between revisions of "Template:10 nm comp header"
| Line 29: | Line 29: | ||
! style="text-align: right;" | Height | ! style="text-align: right;" | Height | ||
|- | |- | ||
| − | ! style="text-align: right;" colspan="2" | Gate | + | ! style="text-align: right;" colspan="2" | Gate Length (L<sub>g</sub>) |
|- | |- | ||
! style="text-align: right;" colspan="2" | Contacted Gate Pitch (CPP) | ! style="text-align: right;" colspan="2" | Contacted Gate Pitch (CPP) | ||
Revision as of 06:29, 6 April 2017
| Process Name | |
|---|---|
| 1st Production | |
| Lithography | Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Transistor | Type |
| Voltage | |
| Fin | Pitch |
| Width | |
| Height | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell | High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell | eDRAM |