Semiconductor & Computer Engineering
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Difference between revisions of "Template:finfet nodes comp"
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-->{{#if: {{{process 6 fab|}}}| {{#ifeq: {{{process 6 fin pitch|}}} | - | | {{!}}{{!}} {{{process 6 fin width|}}} {{#ifeq: {{{process 6 fin pitch Δ|}}} | - | | {{!}}{{!}} {{{process 6 fin width Δ|}}} }} }} }} | -->{{#if: {{{process 6 fab|}}}| {{#ifeq: {{{process 6 fin pitch|}}} | - | | {{!}}{{!}} {{{process 6 fin width|}}} {{#ifeq: {{{process 6 fin pitch Δ|}}} | - | | {{!}}{{!}} {{{process 6 fin width Δ|}}} }} }} }} | ||
|- | |- | ||
| − | | {{{process 1 fin height|}}} {{#ifeq: {{{process 1 fin pitch Δ|}}} | - | | {{!}}{{!}} {{{process 1 fin height Δ|}}} }}<!-- | + | | {{#ifeq: {{{process 1 fin pitch|}}} | - | | {{{process 1 fin height|}}} {{#ifeq: {{{process 1 fin pitch Δ|}}} | - | | {{!}}{{!}} {{{process 1 fin height Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} {{{process 2 fin height|}}} {{#ifeq: {{{process 2 fin pitch Δ|}}} | - | | {{!}}{{!}} {{{process 2 fin height Δ|}}} }} }}<!-- | + | -->{{#if: {{{process 2 fab|}}}| {{#ifeq: {{{process 2 fin pitch|}}} | - | | {{!}}{{!}} {{{process 2 fin height|}}} {{#ifeq: {{{process 2 fin pitch Δ|}}} | - | | {{!}}{{!}} {{{process 2 fin height Δ|}}} }} }} }}<!-- |
| − | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} {{{process 3 fin height|}}} {{#ifeq: {{{process 3 fin pitch Δ|}}} | - | | {{!}}{{!}} {{{process 3 fin height Δ|}}} }} }}<!-- | + | -->{{#if: {{{process 3 fab|}}}| {{#ifeq: {{{process 3 fin pitch|}}} | - | | {{!}}{{!}} {{{process 3 fin height|}}} {{#ifeq: {{{process 3 fin pitch Δ|}}} | - | | {{!}}{{!}} {{{process 3 fin height Δ|}}} }} }} }}<!-- |
| − | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} {{{process 4 fin height|}}} {{#ifeq: {{{process 4 fin pitch Δ|}}} | - | | {{!}}{{!}} {{{process 4 fin height Δ|}}} }} }}<!-- | + | -->{{#if: {{{process 4 fab|}}}| {{#ifeq: {{{process 4 fin pitch|}}} | - | | {{!}}{{!}} {{{process 4 fin height|}}} {{#ifeq: {{{process 4 fin pitch Δ|}}} | - | | {{!}}{{!}} {{{process 4 fin height Δ|}}} }} }} }}<!-- |
| − | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} {{{process 5 fin height|}}} {{#ifeq: {{{process 5 fin pitch Δ|}}} | - | | {{!}}{{!}} {{{process 5 fin height Δ|}}} }} }}<!-- | + | -->{{#if: {{{process 5 fab|}}}| {{#ifeq: {{{process 5 fin pitch|}}} | - | | {{!}}{{!}} {{{process 5 fin height|}}} {{#ifeq: {{{process 5 fin pitch Δ|}}} | - | | {{!}}{{!}} {{{process 5 fin height Δ|}}} }} }} }}<!-- |
| − | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} {{{process 6 fin height|}}} {{#ifeq: {{{process 6 fin pitch Δ|}}} | - | | {{!}}{{!}} {{{process 6 fin height Δ|}}} }} }} | + | -->{{#if: {{{process 6 fab|}}}| {{#ifeq: {{{process 6 fin pitch|}}} | - | | {{!}}{{!}} {{{process 6 fin height|}}} {{#ifeq: {{{process 6 fin pitch Δ|}}} | - | | {{!}}{{!}} {{{process 6 fin height Δ|}}} }} }} }} |
|- | |- | ||
| − | + | | {{{process 1 gate len|}}} || {{#ifeq: {{{process 1 gate len Δ|}}} | - | | {{{process 1 gate len Δ|}}} }}<!-- | |
| − | -->{{#if: {{{process 2 fab|}}} | + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} {{{process 2 gate len|}}} {{#ifeq: {{{process 2 gate len Δ|}}} | - | | {{!}}{{!}} {{{process 2 gate len Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 3 fab|}}} | + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} {{{process 3 gate len|}}} {{#ifeq: {{{process 3 gate len Δ|}}} | - | | {{!}}{{!}} {{{process 3 gate len Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 4 fab|}}} | + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} {{{process 4 gate len|}}} {{#ifeq: {{{process 4 gate len Δ|}}} | - | | {{!}}{{!}} {{{process 4 gate len Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 5 fab|}}} | + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} {{{process 5 gate len|}}} {{#ifeq: {{{process 5 gate len Δ|}}} | - | | {{!}}{{!}} {{{process 5 gate len Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 6 fab|}}} | + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} {{{process 6 gate len|}}} {{#ifeq: {{{process 6 gate len Δ|}}} | - | | {{!}}{{!}} {{{process 6 gate len Δ|}}} }} }} |
|- | |- | ||
| {{{process 1 cpp|}}} || {{#ifeq: {{{process 1 cpp Δ|}}} | - | | {{{process 1 cpp Δ|}}} }}<!-- | | {{{process 1 cpp|}}} || {{#ifeq: {{{process 1 cpp Δ|}}} | - | | {{{process 1 cpp Δ|}}} }}<!-- | ||
Latest revision as of 08:21, 5 April 2017
| Process Name | |
|---|---|
| 1st Production | |
| Litho- graphy |
Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Tran- sistor |
Type |
| Voltage | |
| Fin | Pitch |
| Width | |
| Height | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell |
High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell |
eDRAM |
| Value | |
|---|---|