Semiconductor & Computer Engineering
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Difference between revisions of "Template:finfet nodes comp"
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-->{{#ifeq: {{{process 2 fin pitch|}}} | - | {{!}}{{!}} rowspan="3" colspan="2" style="background: #a3a3a3;" {{!}} N/A | {{!}}{{!}} {{{process 2 fin pitch|}}} {{!}}{{!}} }}<!-- | -->{{#ifeq: {{{process 2 fin pitch|}}} | - | {{!}}{{!}} rowspan="3" colspan="2" style="background: #a3a3a3;" {{!}} N/A | {{!}}{{!}} {{{process 2 fin pitch|}}} {{!}}{{!}} }}<!-- | ||
-->{{#ifeq: {{{process 2 fin pitch Δ|}}} | - | rowspan="{{#ifeq: {{{process 2 gate len Δ|}}} | - | 10 | 3 }}" style="background: #a3a3a3;" {{!}} N/A | {{#ifeq: {{{process 2 fin pitch|}}} | - | | {{{process 2 fin pitch Δ|}}} }} }}<!-- | -->{{#ifeq: {{{process 2 fin pitch Δ|}}} | - | rowspan="{{#ifeq: {{{process 2 gate len Δ|}}} | - | 10 | 3 }}" style="background: #a3a3a3;" {{!}} N/A | {{#ifeq: {{{process 2 fin pitch|}}} | - | | {{{process 2 fin pitch Δ|}}} }} }}<!-- | ||
| − | -->{{# | + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} {{{process 3 fin pitch|}}} {{!}}{{!}} {{#ifeq: {{{process 3 fin pitch Δ|}}} | - | rowspan="{{#ifeq: {{{process 3 gate len Δ|}}} | - | 10 | 3 }}" style="background: #a3a3a3;" {{!}} N/A | {{{process 3 fin pitch Δ|}}} }} }}<!-- |
| − | + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} {{{process 4 fin pitch|}}} {{!}}{{!}} {{#ifeq: {{{process 4 fin pitch Δ|}}} | - | rowspan="{{#ifeq: {{{process 4 gate len Δ|}}} | - | 10 | 3 }}" style="background: #a3a3a3;" {{!}} N/A | {{{process 4 fin pitch Δ|}}} }} }}<!-- | |
| − | -->{{# | + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} {{{process 5 fin pitch|}}} {{!}}{{!}} {{#ifeq: {{{process 5 fin pitch Δ|}}} | - | rowspan="{{#ifeq: {{{process 5 gate len Δ|}}} | - | 10 | 3 }}" style="background: #a3a3a3;" {{!}} N/A | {{{process 5 fin pitch Δ|}}} }} }}<!-- |
| − | + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} {{{process 6 fin pitch|}}} {{!}}{{!}} {{#ifeq: {{{process 6 fin pitch Δ|}}} | - | rowspan="{{#ifeq: {{{process 6 gate len Δ|}}} | - | 10 | 3 }}" style="background: #a3a3a3;" {{!}} N/A | {{{process 6 fin pitch Δ|}}} }} }} | |
| − | -->{{# | ||
| − | |||
| − | -->{{# | ||
| − | |||
|- | |- | ||
| {{{process 1 fin width|}}} {{#ifeq: {{{process 1 fin pitch Δ|}}} | - | | {{!}}{{!}} {{{process 1 fin width Δ|}}} }}<!-- | | {{{process 1 fin width|}}} {{#ifeq: {{{process 1 fin pitch Δ|}}} | - | | {{!}}{{!}} {{{process 1 fin width Δ|}}} }}<!-- | ||
Revision as of 07:58, 5 April 2017
| Process Name | |
|---|---|
| 1st Production | |
| Litho- graphy |
Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Tran- sistor |
Type |
| Voltage | |
| Fin | Pitch |
| Width | |
| Height | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell |
High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell |
eDRAM |
| Value | |||
|---|---|---|---|