Semiconductor & Computer Engineering
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Difference between revisions of "Template:finfet nodes comp"
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-->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} {{{process 6 gate len|}}} {{#ifeq: {{{process 1 gate len Δ|}}} | - | | {{!}}{{!}} {{{process 6 gate len Δ|}}} }} }} | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} {{{process 6 gate len|}}} {{#ifeq: {{{process 1 gate len Δ|}}} | - | | {{!}}{{!}} {{{process 6 gate len Δ|}}} }} }} | ||
|- | |- | ||
| − | | {{{process 1 cpp|}}} || {{{process 1 cpp Δ|}}}<!-- | + | | {{{process 1 cpp|}}} || {{#ifeq: {{{process 1 cpp Δ|}}} | - | | {{{process 1 cpp Δ|}}} }}<!-- |
| − | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} {{{process 2 cpp|}}} {{!}}{{!}} {{{process 2 cpp Δ|}}} }}<!-- | + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} {{{process 2 cpp|}}} {{#ifeq: {{{process 1 cpp Δ|}}} | - | | {{!}}{{!}} {{{process 2 cpp Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} {{{process 3 cpp|}}} {{!}}{{!}} {{{process 3 cpp Δ|}}} }}<!-- | + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} {{{process 3 cpp|}}} {{#ifeq: {{{process 1 cpp Δ|}}} | - | | {{!}}{{!}} {{{process 3 cpp Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} {{{process 4 cpp|}}} {{!}}{{!}} {{{process 4 cpp Δ|}}} }}<!-- | + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} {{{process 4 cpp|}}} {{#ifeq: {{{process 1 cpp Δ|}}} | - | | {{!}}{{!}} {{{process 4 cpp Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} {{{process 5 cpp|}}} {{!}}{{!}} {{{process 5 cpp Δ|}}} }}<!-- | + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} {{{process 5 cpp|}}} {{#ifeq: {{{process 1 cpp Δ|}}} | - | | {{!}}{{!}} {{{process 5 cpp Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} {{{process 6 cpp|}}} {{!}}{{!}} {{{process 6 cpp Δ|}}} }} | + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} {{{process 6 cpp|}}} {{#ifeq: {{{process 1 cpp Δ|}}} | - | | {{!}}{{!}} {{{process 6 cpp Δ|}}} }} }} |
|- | |- | ||
| − | | {{{process 1 mmp|}}} || {{{process 1 mmp Δ|}}}<!-- | + | | {{{process 1 mmp|}}} || {{#ifeq: {{{process 1 mmp Δ|}}} | - | | {{{process 1 mmp Δ|}}} }}<!-- |
| − | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} {{{process 2 mmp|}}} {{!}}{{!}} {{{process 2 mmp Δ|}}} }}<!-- | + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} {{{process 2 mmp|}}} {{#ifeq: {{{process 1 mmp Δ|}}} | - | | {{!}}{{!}} {{{process 2 mmp Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} {{{process 3 mmp|}}} {{!}}{{!}} {{{process 3 mmp Δ|}}} }}<!-- | + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} {{{process 3 mmp|}}} {{#ifeq: {{{process 1 mmp Δ|}}} | - | | {{!}}{{!}} {{{process 3 mmp Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} {{{process 4 mmp|}}} {{!}}{{!}} {{{process 4 mmp Δ|}}} }}<!-- | + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} {{{process 4 mmp|}}} {{#ifeq: {{{process 1 mmp Δ|}}} | - | | {{!}}{{!}} {{{process 4 mmp Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} {{{process 5 mmp|}}} {{!}}{{!}} {{{process 5 mmp Δ|}}} }}<!-- | + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} {{{process 5 mmp|}}} {{#ifeq: {{{process 1 mmp Δ|}}} | - | | {{!}}{{!}} {{{process 5 mmp Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} {{{process 6 mmp|}}} {{!}}{{!}} {{{process 6 mmp Δ|}}} }} | + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} {{{process 6 mmp|}}} {{#ifeq: {{{process 1 mmp Δ|}}} | - | | {{!}}{{!}} {{{process 6 mmp Δ|}}} }} }} |
|- | |- | ||
| {{{process 1 sram hp|}}} || {{{process 1 sram hp Δ|}}}<!-- | | {{{process 1 sram hp|}}} || {{{process 1 sram hp Δ|}}}<!-- | ||
Revision as of 07:24, 5 April 2017
| Process Name | |
|---|---|
| 1st Production | |
| Litho- graphy |
Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Tran- sistor |
Type |
| Voltage | |
| Fin | Pitch |
| Width | |
| Height | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell |
High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell |
eDRAM |
| Value | |
|---|---|