Semiconductor & Computer Engineering
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Difference between revisions of "Template:finfet nodes comp"
| Line 80: | Line 80: | ||
-->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} Value {{!}}{{!}} {{{process 6 delta from|}}} }} | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} Value {{!}}{{!}} {{{process 6 delta from|}}} }} | ||
|- | |- | ||
| − | | {{{process 1 fin pitch|}}} || {{#ifeq: {{{process 1 fin pitch Δ|}}} | - | rowspan="3" style="background: #a3a3a3;" {{!}} N/A | {{{process 1 fin pitch Δ|}}} }}<!-- | + | | {{{process 1 fin pitch|}}} || {{#ifeq: {{{process 1 fin pitch Δ|}}} | - | rowspan="{{#ifeq: {{{process 1 gate len Δ|}}} | - | 10 | 3 }}" style="background: #a3a3a3;" {{!}} N/A | {{{process 1 fin pitch Δ|}}} }}<!-- |
-->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} {{{process 2 fin pitch|}}} {{!}}{{!}} {{#ifeq: {{{process 2 fin pitch Δ|}}} | - | rowspan="3" style="background: #a3a3a3;" {{!}} N/A | {{{process 2 fin pitch Δ|}}} }} }}<!-- | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} {{{process 2 fin pitch|}}} {{!}}{{!}} {{#ifeq: {{{process 2 fin pitch Δ|}}} | - | rowspan="3" style="background: #a3a3a3;" {{!}} N/A | {{{process 2 fin pitch Δ|}}} }} }}<!-- | ||
-->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} {{{process 3 fin pitch|}}} {{!}}{{!}} {{#ifeq: {{{process 3 fin pitch Δ|}}} | - | rowspan="3" style="background: #a3a3a3;" {{!}} N/A | {{{process 3 fin pitch Δ|}}} }} }}<!-- | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} {{{process 3 fin pitch|}}} {{!}}{{!}} {{#ifeq: {{{process 3 fin pitch Δ|}}} | - | rowspan="3" style="background: #a3a3a3;" {{!}} N/A | {{{process 3 fin pitch Δ|}}} }} }}<!-- | ||
| Line 101: | Line 101: | ||
-->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} {{{process 6 fin height|}}} {{#ifeq: {{{process 6 fin pitch Δ|}}} | - | | {{!}}{{!}} {{{process 6 fin height Δ|}}} }} }} | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} {{{process 6 fin height|}}} {{#ifeq: {{{process 6 fin pitch Δ|}}} | - | | {{!}}{{!}} {{{process 6 fin height Δ|}}} }} }} | ||
|- | |- | ||
| − | | {{{process 1 gate len|}}} || {{{process 1 gate len Δ|}}}<!-- | + | | {{{process 1 gate len|}}} || {{#ifeq: {{{process 1 gate len Δ|}}} | - | | {{{process 1 gate len Δ|}}} }}<!-- |
| − | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} {{{process 2 gate len|}}} {{!}}{{!}} {{{process 2 gate len Δ|}}} }}<!-- | + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} {{{process 2 gate len|}}} {{#ifeq: {{{process 1 gate len Δ|}}} | - | | {{!}}{{!}} {{{process 2 gate len Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} {{{process 3 gate len|}}} {{!}}{{!}} {{{process 3 gate len Δ|}}} }}<!-- | + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} {{{process 3 gate len|}}} {{#ifeq: {{{process 1 gate len Δ|}}} | - | | {{!}}{{!}} {{{process 3 gate len Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} {{{process 4 gate len|}}} {{!}}{{!}} {{{process 4 gate len Δ|}}} }}<!-- | + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} {{{process 4 gate len|}}} {{#ifeq: {{{process 1 gate len Δ|}}} | - | | {{!}}{{!}} {{{process 4 gate len Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} {{{process 5 gate len|}}} {{!}}{{!}} {{{process 5 gate len Δ|}}} }}<!-- | + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} {{{process 5 gate len|}}} {{#ifeq: {{{process 1 gate len Δ|}}} | - | | {{!}}{{!}} {{{process 5 gate len Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} {{{process 6 gate len|}}} {{!}}{{!}} {{{process 6 gate len Δ|}}} }} | + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} {{{process 6 gate len|}}} {{#ifeq: {{{process 1 gate len Δ|}}} | - | | {{!}}{{!}} {{{process 6 gate len Δ|}}} }} }} |
|- | |- | ||
| {{{process 1 cpp|}}} || {{{process 1 cpp Δ|}}}<!-- | | {{{process 1 cpp|}}} || {{{process 1 cpp Δ|}}}<!-- | ||
Revision as of 06:17, 5 April 2017
| Process Name | |
|---|---|
| 1st Production | |
| Lithography | Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Transistor | Type |
| Voltage | |
| Fin | Pitch |
| Width | |
| Height | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell | High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell | eDRAM |
| Value | |
|---|---|