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Difference between revisions of "Template:finfet nodes comp"

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-->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} {{{process 4 fin pitch|}}} {{!}}{{!}} {{#ifeq: {{{process 4 fin pitch Δ|}}} | - | rowspan="3" style="background: #a3a3a3;" {{!}} N/A | {{{process 4 fin pitch Δ|}}} }} }}<!--
 
-->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} {{{process 4 fin pitch|}}} {{!}}{{!}} {{#ifeq: {{{process 4 fin pitch Δ|}}} | - | rowspan="3" style="background: #a3a3a3;" {{!}} N/A | {{{process 4 fin pitch Δ|}}} }} }}<!--
 
-->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} {{{process 5 fin pitch|}}} {{!}}{{!}} {{#ifeq: {{{process 5 fin pitch Δ|}}} | - | rowspan="3" style="background: #a3a3a3;" {{!}} N/A | {{{process 5 fin pitch Δ|}}} }} }}<!--
 
-->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} {{{process 5 fin pitch|}}} {{!}}{{!}} {{#ifeq: {{{process 5 fin pitch Δ|}}} | - | rowspan="3" style="background: #a3a3a3;" {{!}} N/A | {{{process 5 fin pitch Δ|}}} }} }}<!--
−
-->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} {{{process 6 fin pitch|}}} {{!}}{{!}} {{#ifeq: {{{process 6 fin pitch Δ|}}} | - | rowspan="3" style="background: #a3a3a3;" {{!}} N/A | {{{process 6 fin pitch Δ|}}} }} }}<!--
+
-->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} {{{process 6 fin pitch|}}} {{!}}{{!}} {{#ifeq: {{{process 6 fin pitch Δ|}}} | - | rowspan="3" style="background: #a3a3a3;" {{!}} N/A | {{{process 6 fin pitch Δ|}}} }} }}
 
|-
 
|-
 
| {{{process 1 fin width|}}} || {{{process 1 fin width Δ|}}}<!--
 
| {{{process 1 fin width|}}} || {{{process 1 fin width Δ|}}}<!--

Revision as of 04:26, 5 April 2017

 
Process Name
1st Production
Litho-
graphy 		Lithography
Immersion
Exposure
Wafer Type
Size
Tran-
sistor 		Type
Voltage
 
Fin Pitch
Width
Height
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM
bitcell 		High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM
bitcell 		eDRAM
Value
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