From WikiChip
Difference between revisions of "Template:finfet nodes comp"

Line 85: Line 85:
 
-->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} {{{process 4 fin pitch|}}} {{!}}{{!}} {{#ifeq: {{{process 4 fin pitch Δ|}}} | - | rowspan="3" style="background: #a3a3a3;" {{!}} N/A | {{{process 4 fin pitch Δ|}}} }} }}<!--
 
-->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} {{{process 4 fin pitch|}}} {{!}}{{!}} {{#ifeq: {{{process 4 fin pitch Δ|}}} | - | rowspan="3" style="background: #a3a3a3;" {{!}} N/A | {{{process 4 fin pitch Δ|}}} }} }}<!--
 
-->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} {{{process 5 fin pitch|}}} {{!}}{{!}} {{#ifeq: {{{process 5 fin pitch Δ|}}} | - | rowspan="3" style="background: #a3a3a3;" {{!}} N/A | {{{process 5 fin pitch Δ|}}} }} }}<!--
 
-->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} {{{process 5 fin pitch|}}} {{!}}{{!}} {{#ifeq: {{{process 5 fin pitch Δ|}}} | - | rowspan="3" style="background: #a3a3a3;" {{!}} N/A | {{{process 5 fin pitch Δ|}}} }} }}<!--
−
-->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} {{{process 6 fin pitch|}}} {{!}}{{!}} {{#ifeq: {{{process 6 fin pitch Δ|}}} | - | rowspan="3" style="background: #a3a3a3;" {{!}} N/A | {{{process 6 fin pitch Δ|}}} }} }}<!--
+
-->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} {{{process 6 fin pitch|}}} {{!}}{{!}} {{#ifeq: {{{process 6 fin pitch Δ|}}} | - | rowspan="3" style="background: #a3a3a3;" {{!}} N/A | {{{process 6 fin pitch Δ|}}} }} }}
 
|-
 
|-
 
| {{{process 1 fin width|}}} || {{{process 1 fin width Δ|}}}<!--
 
| {{{process 1 fin width|}}} || {{{process 1 fin width Δ|}}}<!--

Revision as of 03:26, 5 April 2017

 
Process Name
1st Production
Lithography Lithography
Immersion
Exposure
Wafer Type
Size
Transistor Type
Voltage
 
Fin Pitch
Width
Height
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcell eDRAM
Value
Retrieved from "https://en.wikichip.org/w/index.php?title=Template:finfet_nodes_comp&oldid=40873"