Semiconductor & Computer Engineering
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Difference between revisions of "Template:finfet nodes comp"
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| {{{process 1 fin width|}}} || {{{process 1 fin width Δ|}}}<!-- | | {{{process 1 fin width|}}} || {{{process 1 fin width Δ|}}}<!-- | ||
| − | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} {{!}} {{{process 2 fin width|}}} | + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} {{!}} {{{process 2 fin width|}}} {{!}}{{!}} {{{process 2 fin width Δ|}}} }}<!-- |
-->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} {{!}} {{{process 3 fin width|}}} {{!}}{{!}} {{{process 3 fin width Δ|}}} }}<!-- | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} {{!}} {{{process 3 fin width|}}} {{!}}{{!}} {{{process 3 fin width Δ|}}} }}<!-- | ||
-->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} {{!}} {{{process 4 fin width|}}} {{!}}{{!}} {{{process 4 fin width Δ|}}} }}<!-- | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} {{!}} {{{process 4 fin width|}}} {{!}}{{!}} {{{process 4 fin width Δ|}}} }}<!-- | ||
Revision as of 04:18, 5 April 2017
| Process Name | |
|---|---|
| 1st Production | |
| Litho- graphy |
Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Tran- sistor |
Type |
| Voltage | |
| Fin | Pitch |
| Width | |
| Height | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell |
High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell |
eDRAM |
| Value | |
|---|---|