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Difference between revisions of "Template:finfet nodes comp"
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-->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 volt|}}} }} | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 volt|}}} }} | ||
|- | |- | ||
− | ! | + | ! Value !! {{{process 1 delta from|}}}<!-- |
-->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} Value {{!}}{{!}} colspan="2" {{!}} {{{process 2 delta from|}}} }}<!-- | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} Value {{!}}{{!}} colspan="2" {{!}} {{{process 2 delta from|}}} }}<!-- | ||
-->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} Value {{!}}{{!}} colspan="2" {{!}} {{{process 3 delta from|}}} }}<!-- | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} Value {{!}}{{!}} colspan="2" {{!}} {{{process 3 delta from|}}} }}<!-- |
Revision as of 02:19, 5 April 2017
Process Name | |
---|---|
1st Production | |
Lithography | Lithography |
Immersion | |
Exposure | |
Wafer | Type |
Size | |
Transistor | Type |
Voltage | |
Fin | Pitch |
Width | |
Height | |
Gate Length (Lg) | |
Contacted Gate Pitch (CPP) | |
Minimum Metal Pitch (MMP) | |
SRAM bitcell | High-Perf (HP) |
High-Density (HD) | |
Low-Voltage (LV) | |
DRAM bitcell | eDRAM |
Value | |||||
---|---|---|---|---|---|