Semiconductor & Computer Engineering
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Difference between revisions of "Template:finfet nodes comp"
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-->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 fab|}}} }} | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 fab|}}} }} | ||
|- style="text-align: center;" | |- style="text-align: center;" | ||
| − | ! colspan="2" | {{{process 1 | + | ! colspan="2" | {{{process 1 name|}}}<!-- |
-->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 name|}}} }}<!-- | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 name|}}} }}<!-- | ||
-->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 name|}}} }}<!-- | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 name|}}} }}<!-- | ||
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-->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 name|}}} }} | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 name|}}} }} | ||
|- style="text-align: center;" | |- style="text-align: center;" | ||
| − | ! colspan="2" | {{{process 1 | + | ! colspan="2" | {{{process 1 date|}}}<!-- |
-->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 date|}}} }}<!-- | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 date|}}} }}<!-- | ||
-->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 date|}}} }}<!-- | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 date|}}} }}<!-- | ||
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-->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 date|}}} }} | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 date|}}} }} | ||
|- style="text-align: center;" | |- style="text-align: center;" | ||
| − | ! colspan="2" | {{{process 1 | + | ! colspan="2" | {{{process 1 lith|}}}<!-- |
-->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 lith|}}} }}<!-- | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 lith|}}} }}<!-- | ||
-->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 lith|}}} }}<!-- | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 lith|}}} }}<!-- | ||
Revision as of 02:40, 5 April 2017
| Process Name | |
|---|---|
| 1st Production | |
| Litho- graphy |
Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Tran- sistor |
Type |
| Voltage | |
| Fin | Pitch |
| Width | |
| Height | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell |
High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell |
eDRAM |
| Value | Value | Value | |||
|---|---|---|---|---|---|