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Difference between revisions of "Template:finfet nodes comp"

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{| class="wikitable" style="margin:0; {{{style|}}}"
 
{| class="wikitable" style="margin:0; {{{style|}}}"
 
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|- style="text-align: center;"
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! colspan="2" | {{{process 1 fab|}}} || colspan="2" | {{{process 2 fab|}}} || colspan="2" | {{{process 3 fab|}}}
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! colspan="2" | {{{process 1 fab|}}}<!--
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-->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 fab|}}} }}<!--
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-->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 fab|}}} }}<!--
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-->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 fab|}}} }}<!--
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-->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 fab|}}} }}
 
|- style="text-align: center;"
 
|- style="text-align: center;"
 
| colspan="2" | {{{process 1 name|}}} || colspan="2" | {{{process 2 name|}}} || colspan="2" | {{{process 3 name|}}}
 
| colspan="2" | {{{process 1 name|}}} || colspan="2" | {{{process 2 name|}}} || colspan="2" | {{{process 3 name|}}}

Revision as of 02:31, 5 April 2017

 
Process Name
1st Production
Lithography Lithography
Immersion
Exposure
Wafer Type
Size
Transistor Type
Voltage
 
Fin Pitch
Width
Height
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcell eDRAM
Value Value Value
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