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Difference between revisions of "Template:10 nm comp header"
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! style="text-align: right;" colspan="2" | 1st Production | ! style="text-align: right;" colspan="2" | 1st Production | ||
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+ | ! style="text-align: center;" rowspan="3" | Lithography || style="text-align: right;" | Lithography | ||
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+ | ! style="text-align: right;" | Immersion | ||
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+ | ! style="text-align: right;" | Exposure | ||
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! style="text-align: center;" rowspan="2" | Wafer || style="text-align: right;" | Type | ! style="text-align: center;" rowspan="2" | Wafer || style="text-align: right;" | Type |
Revision as of 23:21, 4 April 2017
Process Name | |
---|---|
1st Production | |
Lithography | Lithography |
Immersion | |
Exposure | |
Wafer | Type |
Size | |
Transistor | Type |
Voltage | |
Fin | Pitch |
Width | |
Height | |
Gate Pitch (Lg) | |
Contacted Gate Pitch (CPP) | |
Interconnect Pitch (M1P) | |
SRAM bitcell | High-Perf (HP) |
High-Density (HD) | |
Low-Voltage (LV) | |
DRAM bitcell | eDRAM |