Difference between revisions of "Template:finfet nodes comp"

Revision as of 23:53, 4 April 2017


Process Name
1st Production
Litho- graphy	Lithography
	Immersion
	Exposure
Wafer	Type
Wafer	Size
Tran- sistor	Type
Tran- sistor	Voltage

Fin	Pitch
	Width
	Height
Gate Length (L_g)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell	High-Perf (HP)
	High-Density (HD)
	Low-Voltage (LV)
DRAM bitcell	eDRAM

 {{{process 1 fab}}} 
 {{{process 2 fab}}} 
 {{{process 3 fab}}}

 {{{process 1 name}}} 
 {{{process 2 name}}} 
 {{{process 3 name}}}

 {{{process 1 date}}} 
 {{{process 2 date}}} 
 {{{process 3 date}}}

 {{{process 1 wafer type}}} 
 {{{process 2 wafer type}}} 
 {{{process 3 wafer type}}}

 {{{process 1 wafer size}}} 
 {{{process 2 wafer size}}} 
 {{{process 3 wafer size}}}

 {{{process 1 wafer type}}} 
 {{{process 2 wafer type}}} 
 {{{process 3 wafer type}}}

 {{{process 1 volt}}} 
 {{{process 2 volt}}} 
 {{{process 3 volt}}}

 Value 
 {{{process 1 delta from}}} 
 Value 
 {{{process 2 delta from}}} 
 Value 
 {{{process 3 delta from}}}

 {{{process 1 fin pitch}}} 
 {{{process 1 fin pitch Δ}}} 
 {{{process 2 fin pitch}}} 
 {{{process 2 fin pitch Δ}}} 
 {{{process 3 fin pitch}}} 
 {{{process 3 fin pitch Δ}}}

 {{{process 1 fin width}}} 
 {{{process 1 fin width Δ}}} 
 {{{process 2 fin width}}} 
 {{{process 2 fin width Δ}}} 
 {{{process 3 fin width}}} 
 {{{process 3 fin width Δ}}}

 {{{process 1 fin height}}} 
 {{{process 1 fin height Δ}}} 
 {{{process 2 fin height}}} 
 {{{process 2 fin height Δ}}} 
 {{{process 3 fin height}}} 
 {{{process 3 fin height Δ}}}

 {{{process 1 gate len}}} 
 {{{process 1 gate len Δ}}} 
 {{{process 2 gate len}}} 
 {{{process 2 gate len Δ}}} 
 {{{process 3 gate len}}} 
 {{{process 3 gate len Δ}}}

 {{{process 1 cpp}}} 
 {{{process 1 cpp Δ}}} 
 {{{process 2 cpp}}} 
 {{{process 2 cpp Δ}}} 
 {{{process 3 cpp}}} 
 {{{process 3 cpp Δ}}}

 {{{process 1 mmp}}} 
 {{{process 1 mmp Δ}}} 
 {{{process 2 mmp}}} 
 {{{process 2 mmp Δ}}} 
 {{{process 3 mmp}}} 
 {{{process 3 mmp Δ}}}

 {{{process 1 sram hp}}} 
 {{{process 1 sram hp Δ}}} 
 {{{process 2 sram hp}}} 
 {{{process 2 sram hp Δ}}} 
 {{{process 3 sram hp}}} 
 {{{process 3 sram hp Δ}}}

 {{{process 1 sram hd}}} 
 {{{process 1 sram hd Δ}}} 
 {{{process 2 sram hd}}} 
 {{{process 2 sram hd Δ}}} 
 {{{process 3 sram hd}}} 
 {{{process 3 sram hd Δ}}}

 {{{process 1 sram lv}}} 
 {{{process 1 sram lv Δ}}} 
 {{{process 2 sram lv}}} 
 {{{process 2 sram lv Δ}}} 
 {{{process 3 sram lv}}} 
 {{{process 3 sram lv Δ}}}

 {{{process 1 dram}}} 
 {{{process 1 dram Δ}}} 
 {{{process 2 dram}}} 
 {{{process 2 dram Δ}}} 
 {{{process 3 dram}}} 
 {{{process 3 dram Δ}}}

@@ Line 3: / Line 3: @@
 {| class="wikitable" style="margin:0; {{{style|}}}"
 |- style="text-align: center;"
-| colspan="2" | {{{process 1 fab|&nbsp;}}} || colspan="2" | {{{process 2 fab|&nbsp;}}} || colspan="2" | {{{process 3 fab|&nbsp;}}}
+| colspan="2" | {{{process 1 fab}}} || colspan="2" | {{{process 2 fab}}} || colspan="2" | {{{process 3 fab}}}
 |- style="text-align: center;"
-| colspan="2" | {{{process 1 name|&nbsp;}}} || colspan="2" | {{{process 2 name|&nbsp;}}} || colspan="2" | {{{process 3 name|&nbsp;}}}
+| colspan="2" | {{{process 1 name}}} || colspan="2" | {{{process 2 name}}} || colspan="2" | {{{process 3 name}}}
 |- style="text-align: center;"
-| colspan="2" | {{{process 1 date|&nbsp;}}} || colspan="2" | {{{process 2 date|&nbsp;}}} || colspan="2" | {{{process 3 date|&nbsp;}}}
+| colspan="2" | {{{process 1 date}}} || colspan="2" | {{{process 2 date}}} || colspan="2" | {{{process 3 date}}}
 |- style="text-align: center;"
-| colspan="2" | {{{process 1 wafer type|&nbsp;}}} || colspan="2" | {{{process 2 wafer type|&nbsp;}}} || colspan="2" | {{{process 3 wafer type|&nbsp;}}}
+| colspan="2" | {{{process 1 wafer type}}} || colspan="2" | {{{process 2 wafer type}}} || colspan="2" | {{{process 3 wafer type}}}
 |- style="text-align: center;"
-| colspan="2" | {{{process 1 wafer size|&nbsp;}}} || colspan="2" | {{{process 2 wafer size|&nbsp;}}} || colspan="2" | {{{process 3 wafer size|&nbsp;}}}
+| colspan="2" | {{{process 1 wafer size}}} || colspan="2" | {{{process 2 wafer size}}} || colspan="2" | {{{process 3 wafer size}}}
 |- style="text-align: center;"
-| colspan="2" | {{{process 1 wafer type|&nbsp;}}} || colspan="2" | {{{process 2 wafer type|&nbsp;}}} || colspan="2" | {{{process 3 wafer type|&nbsp;}}}
+| colspan="2" | {{{process 1 wafer type}}} || colspan="2" | {{{process 2 wafer type}}} || colspan="2" | {{{process 3 wafer type}}}
 |- style="text-align: center;"
-| colspan="2" | {{{process 1 volt|&nbsp;}}} || colspan="2" | {{{process 2 volt|&nbsp;}}} || colspan="2" | {{{process 3 volt|&nbsp;}}}
+| colspan="2" | {{{process 1 volt}}} || colspan="2" | {{{process 2 volt}}} || colspan="2" | {{{process 3 volt}}}
 |-
-! Value !! {{{process 1 delta from|&nbsp;}}} !! Value !! {{{process 2 delta from|&nbsp;}}} !! Value !! {{{process 3 delta from|&nbsp;}}}
+! Value !! {{{process 1 delta from}}} !! Value !! {{{process 2 delta from}}} !! Value !! {{{process 3 delta from}}}
 |-
-| {{{process 1 fin pitch|&nbsp;}}} || {{{process 1 fin pitch Δ|&nbsp;}}} || {{{process 2 fin pitch|&nbsp;}}} || {{{process 2 fin pitch Δ|&nbsp;}}} || {{{process 3 fin pitch|&nbsp;}}} || {{{process 3 fin pitch Δ|&nbsp;}}}
+| {{{process 1 fin pitch}}} || {{{process 1 fin pitch Δ}}} || {{{process 2 fin pitch}}} || {{{process 2 fin pitch Δ}}} || {{{process 3 fin pitch}}} || {{{process 3 fin pitch Δ}}}
 |-
-| {{{process 1 fin width|&nbsp;}}} || {{{process 1 fin width Δ|&nbsp;}}} || {{{process 2 fin width|&nbsp;}}} || {{{process 2 fin width Δ|&nbsp;}}} || {{{process 3 fin width|&nbsp;}}} || {{{process 3 fin width Δ|&nbsp;}}}
+| {{{process 1 fin width}}} || {{{process 1 fin width Δ}}} || {{{process 2 fin width}}} || {{{process 2 fin width Δ}}} || {{{process 3 fin width}}} || {{{process 3 fin width Δ}}}
 |-
-| {{{process 1 fin height|&nbsp;}}} || {{{process 1 fin height Δ|&nbsp;}}} || {{{process 2 fin height|&nbsp;}}} || {{{process 2 fin height Δ|&nbsp;}}} || {{{process 3 fin height|&nbsp;}}} || {{{process 3 fin height Δ|&nbsp;}}}
+| {{{process 1 fin height}}} || {{{process 1 fin height Δ}}} || {{{process 2 fin height}}} || {{{process 2 fin height Δ}}} || {{{process 3 fin height}}} || {{{process 3 fin height Δ}}}
 |-
-| {{{process 1 gate len|&nbsp;}}} || {{{process 1 gate len Δ|&nbsp;}}} || {{{process 2 gate len|&nbsp;}}} || {{{process 2 gate len Δ|&nbsp;}}} || {{{process 3 gate len|&nbsp;}}} || {{{process 3 gate len Δ|&nbsp;}}}
+| {{{process 1 gate len}}} || {{{process 1 gate len Δ}}} || {{{process 2 gate len}}} || {{{process 2 gate len Δ}}} || {{{process 3 gate len}}} || {{{process 3 gate len Δ}}}
 |-
-| {{{process 1 cpp|&nbsp;}}} || {{{process 1 cpp Δ|&nbsp;}}} || {{{process 2 cpp|&nbsp;}}} || {{{process 2 cpp Δ|&nbsp;}}} || {{{process 3 cpp|&nbsp;}}} || {{{process 3 cpp Δ|&nbsp;}}}
+| {{{process 1 cpp}}} || {{{process 1 cpp Δ}}} || {{{process 2 cpp}}} || {{{process 2 cpp Δ}}} || {{{process 3 cpp}}} || {{{process 3 cpp Δ}}}
 |-
-| {{{process 1 mmp|&nbsp;}}} || {{{process 1 mmp Δ|&nbsp;}}} || {{{process 2 mmp|&nbsp;}}} || {{{process 2 mmp Δ|&nbsp;}}} || {{{process 3 mmp|&nbsp;}}} || {{{process 3 mmp Δ|&nbsp;}}}
+| {{{process 1 mmp}}} || {{{process 1 mmp Δ}}} || {{{process 2 mmp}}} || {{{process 2 mmp Δ}}} || {{{process 3 mmp}}} || {{{process 3 mmp Δ}}}
 |-
-| {{{process 1 sram hp|&nbsp;}}} || {{{process 1 sram hp Δ|&nbsp;}}} || {{{process 2 sram hp|&nbsp;}}} || {{{process 2 sram hp Δ|&nbsp;}}} || {{{process 3 sram hp|&nbsp;}}} || {{{process 3 sram hp Δ|&nbsp;}}}
+| {{{process 1 sram hp}}} || {{{process 1 sram hp Δ}}} || {{{process 2 sram hp}}} || {{{process 2 sram hp Δ}}} || {{{process 3 sram hp}}} || {{{process 3 sram hp Δ}}}
 |-
-| {{{process 1 sram hd|&nbsp;}}} || {{{process 1 sram hd Δ|&nbsp;}}} || {{{process 2 sram hd|&nbsp;}}} || {{{process 2 sram hd Δ|&nbsp;}}} || {{{process 3 sram hd|&nbsp;}}} || {{{process 3 sram hd Δ|&nbsp;}}}
+| {{{process 1 sram hd}}} || {{{process 1 sram hd Δ}}} || {{{process 2 sram hd}}} || {{{process 2 sram hd Δ}}} || {{{process 3 sram hd}}} || {{{process 3 sram hd Δ}}}
 |-
-| {{{process 1 sram lv|&nbsp;}}} || {{{process 1 sram lv Δ|&nbsp;}}} || {{{process 2 sram lv|&nbsp;}}} || {{{process 2 sram lv Δ|&nbsp;}}} || {{{process 3 sram lv|&nbsp;}}} || {{{process 3 sram lv Δ|&nbsp;}}}
+| {{{process 1 sram lv}}} || {{{process 1 sram lv Δ}}} || {{{process 2 sram lv}}} || {{{process 2 sram lv Δ}}} || {{{process 3 sram lv}}} || {{{process 3 sram lv Δ}}}
 |-
-| {{{process 1 dram|&nbsp;}}} || {{{process 1 dram Δ|&nbsp;}}} || {{{process 2 dram|&nbsp;}}} || {{{process 2 dram Δ|&nbsp;}}} || {{{process 3 dram|&nbsp;}}} || {{{process 3 dram Δ|&nbsp;}}}
+| {{{process 1 dram}}} || {{{process 1 dram Δ}}} || {{{process 2 dram}}} || {{{process 2 dram Δ}}} || {{{process 3 dram}}} || {{{process 3 dram Δ}}}
 |}

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas

Samsung

Revision as of 23:53, 4 April 2017

Value	{{{process 1 delta from}}}	Value	{{{process 2 delta from}}}	Value	{{{process 3 delta from}}}
{{{process 1 fab}}}		{{{process 2 fab}}}		{{{process 3 fab}}}
{{{process 1 name}}}		{{{process 2 name}}}		{{{process 3 name}}}
{{{process 1 date}}}		{{{process 2 date}}}		{{{process 3 date}}}
{{{process 1 wafer type}}}		{{{process 2 wafer type}}}		{{{process 3 wafer type}}}
{{{process 1 wafer size}}}		{{{process 2 wafer size}}}		{{{process 3 wafer size}}}
{{{process 1 wafer type}}}		{{{process 2 wafer type}}}		{{{process 3 wafer type}}}
{{{process 1 volt}}}		{{{process 2 volt}}}		{{{process 3 volt}}}
{{{process 1 fin pitch}}}	{{{process 1 fin pitch Δ}}}	{{{process 2 fin pitch}}}	{{{process 2 fin pitch Δ}}}	{{{process 3 fin pitch}}}	{{{process 3 fin pitch Δ}}}
{{{process 1 fin width}}}	{{{process 1 fin width Δ}}}	{{{process 2 fin width}}}	{{{process 2 fin width Δ}}}	{{{process 3 fin width}}}	{{{process 3 fin width Δ}}}
{{{process 1 fin height}}}	{{{process 1 fin height Δ}}}	{{{process 2 fin height}}}	{{{process 2 fin height Δ}}}	{{{process 3 fin height}}}	{{{process 3 fin height Δ}}}
{{{process 1 gate len}}}	{{{process 1 gate len Δ}}}	{{{process 2 gate len}}}	{{{process 2 gate len Δ}}}	{{{process 3 gate len}}}	{{{process 3 gate len Δ}}}
{{{process 1 cpp}}}	{{{process 1 cpp Δ}}}	{{{process 2 cpp}}}	{{{process 2 cpp Δ}}}	{{{process 3 cpp}}}	{{{process 3 cpp Δ}}}
{{{process 1 mmp}}}	{{{process 1 mmp Δ}}}	{{{process 2 mmp}}}	{{{process 2 mmp Δ}}}	{{{process 3 mmp}}}	{{{process 3 mmp Δ}}}
{{{process 1 sram hp}}}	{{{process 1 sram hp Δ}}}	{{{process 2 sram hp}}}	{{{process 2 sram hp Δ}}}	{{{process 3 sram hp}}}	{{{process 3 sram hp Δ}}}
{{{process 1 sram hd}}}	{{{process 1 sram hd Δ}}}	{{{process 2 sram hd}}}	{{{process 2 sram hd Δ}}}	{{{process 3 sram hd}}}	{{{process 3 sram hd Δ}}}
{{{process 1 sram lv}}}	{{{process 1 sram lv Δ}}}	{{{process 2 sram lv}}}	{{{process 2 sram lv Δ}}}	{{{process 3 sram lv}}}	{{{process 3 sram lv Δ}}}
{{{process 1 dram}}}	{{{process 1 dram Δ}}}	{{{process 2 dram}}}	{{{process 2 dram Δ}}}	{{{process 3 dram}}}	{{{process 3 dram Δ}}}